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公开(公告)号：US11960739B1
公开(公告)日：2024-04-16
申请号：US17929191
申请日：2022-09-01
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Jingkui Zheng , David A. Knopf , Satish B. Dulam , Kai Lun Hsiung , Venkata Ramana Malladi , Rahul Ranjan
CPC classification number: G06F3/0632 , G06F3/0614 , G06F3/0658 , G06F3/0673 , G11C7/22 , G11C2207/2254
Abstract: The present disclosure is directed to a reference voltage calibration. An apparatus includes a memory and a memory controller including a calibration circuit configured to perform a reference voltage calibration to determine a reference voltage used to distinguish between logic values read from the memory. The reference voltage calibration comprises performing horizontal calibrations at different reference voltage values to determine a range of delay values applied to a data strobe signal at which valid data is read from the memory. The calibration includes determining scores corresponding to ones of the plurality of horizontal calibrations in which a score for a particular one of the plurality of horizontal calibrations is based on a corresponding range of delay values and a reference voltage margin. Thereafter, the calibration circuit selects a calibrated reference voltage based on the scores corresponding to ones of the plurality of horizontal calibrations.
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公开(公告)号：US11501820B2
公开(公告)日：2022-11-15
申请号：US17181979
申请日：2021-02-22
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Kai Lun Hsiung , Rakesh L. Notani , Venkata Ramana Malladi , John H. Kelm , Taehyun Kim
IPC: G11C11/00 , G11C11/4074 , G11C11/4096 , G06F3/06 , G11C11/4076
Abstract: A method and apparatus for selective reference voltage calibration in a memory subsystem is disclosed. A memory subsystem includes a memory coupled to a memory controller. The memory controller may operate in one of a number of different performance states. The memory controller further includes a calibration circuit configured to perform reference voltage calibrations for the various ones of the performance states to determine corresponding reference voltages. For a performance state change from an initial performance state to a final performance state, via an intermediate performance state, the memory controller is configured to transition to the intermediate performance state without causing the calibration circuit to perform a reference voltage calibration in that state. Thereafter, the memory controller transitions to the final performance state.
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公开(公告)号：US20200057579A1
公开(公告)日：2020-02-20
申请号：US16104307
申请日：2018-08-17
Applicant: Apple Inc.
Inventor： Gregory S. Mathews , Kai Lun Hsiung , Lakshmi Narasimha Murthy Nukala , Peter Fu , Rakesh L. Notani , Sukalpa Biswas , Thejasvi Magudilu Vijayaraj , Yanzhe Liu , Shane J. Keil
IPC: G06F3/06
Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller implements a per-bank priority-based arbitration scheme for different types of memory traffic (e.g., with different quality of service parameters). In some embodiments, the memory controller is configured to provide per-bank overrides to the arbitration scheme based on latency tolerance reported by one or more requesters sending a particular type of memory traffic. Various techniques disclosed herein may improve performance, improve fairness among different types of memory traffic, and/or reduce power consumption.
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公开(公告)号：US10545701B1
公开(公告)日：2020-01-28
申请号：US16104307
申请日：2018-08-17
Applicant: Apple Inc.
Inventor： Gregory S. Mathews , Kai Lun Hsiung , Lakshmi Narasimha Murthy Nukala , Peter Fu , Rakesh L. Notani , Sukalpa Biswas , Thejasvi Magudilu Vijayaraj , Yanzhe Liu , Shane J. Keil
IPC: G06F3/06
Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller implements a per-bank priority-based arbitration scheme for different types of memory traffic (e.g., with different quality of service parameters). In some embodiments, the memory controller is configured to provide per-bank overrides to the arbitration scheme based on latency tolerance reported by one or more requesters sending a particular type of memory traffic. Various techniques disclosed herein may improve performance, improve fairness among different types of memory traffic, and/or reduce power consumption.
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公开(公告)号：US20180074743A1
公开(公告)日：2018-03-15
申请号：US15263833
申请日：2016-09-13
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Liang Deng , Kai Lun Hsiung , Manu Gulati , Rakesh L. Notani , Sukalpa Biswas , Venkata Ramana Malladi , Gregory S. Mathews , Enming Zheng , Fabien S. Faure
CPC classification number: G06F3/0634 , G06F1/08 , G06F1/324 , G06F3/0625 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G06F3/0683 , G06F13/1689 , G06F13/4243 , Y02D10/14 , Y02D10/151
Abstract: Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.
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Patent Agency Ranking
公开(公告)号：US20180061465A1
公开(公告)日：2018-03-01
申请号：US15249962
申请日：2016-08-29
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Rakesh L. Notani , Kai Lun Hsiung , Alma L. Juarez Dominguez
CPC classification number: G11C7/22 , G11C7/10 , G11C7/222 , G11C11/401 , G11C29/023 , G11C29/028 , G11C29/12015
Abstract: A system and method for calibrating memory using credit-based segmentation control is disclosed. A memory and a memory controller coupled thereto. The memory controller includes a calibration circuit configured to calibrate a data strobe signal conveyed to/from the memory. The calibration may be subdivided, in time, into a number of segments. The memory controller also includes a credit circuit configured to provide a condition code to the calibration circuit. The condition code may be indicative of an amount of time a request has been pending, or how many request are pending. If to the condition code indicates that a request has been pending for more than a certain amount of time, the calibration may be terminated.
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公开(公告)号：US20240061617A1
公开(公告)日：2024-02-22
申请号：US18497883
申请日：2023-10-30
Applicant: Apple Inc.
Inventor： Gregory S. Mathews , Kai Lun Hsiung , Lakshmi Narasimha Murthy Nukala , Shane J. Keil , Thejasvi Magudilu Vijayaraj , Yanzhe Liu , Tao Zhang
CPC classification number: G06F3/0659 , G06F3/0611 , G06F13/1605 , G06F3/0644 , G06F3/0673
Abstract: Systems, apparatuses, and methods for addressing bank hotspotting are described. A computing system includes a memory controller with an arbiter for determining how to arbitrate access to one or more memory device(s) for received requests. The arbiter categorizes each request in a manner that helps to ensure fair virtual channel distribution across the banks of the memory device(s). The category system includes bank hotspotting functions to give banks that have more requests more chances to go over banks with fewer requests. The category system is implemented proportionally with more category credits given to banks with higher bank depths within the virtual channel.
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公开(公告)号：US20220357879A1
公开(公告)日：2022-11-10
申请号：US17313811
申请日：2021-05-06
Applicant: Apple Inc.
Inventor： Gregory S. Mathews , Kai Lun Hsiung , Lakshmi Narasimha Murthy Nukala , Shane J. Keil , Thejasvi Magudilu Vijayaraj , Yanzhe Liu , Tao Zhang
Abstract: Systems, apparatuses, and methods for addressing bank hotspotting are described. A computing system includes a memory controller with an arbiter for determining how to arbitrate access to one or more memory device(s) for received requests. The arbiter categorizes each request in a manner that helps to ensure fair virtual channel distribution across the banks of the memory device(s). The category system includes bank hotspotting functions to give banks that have more requests more chances to go over banks with fewer requests. The category system is implemented proportionally with more category credits given to banks with higher bank depths within the virtual channel.
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公开(公告)号：US20220189519A1
公开(公告)日：2022-06-16
申请号：US17646741
申请日：2022-01-03
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Rakesh L. Notani , Kai Lun Hsiung , Venkata Ramana Malladi , Rahul Ranjan , Naveen Kumar Korada
Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.
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公开(公告)号：US11221798B2
公开(公告)日：2022-01-11
申请号：US16751975
申请日：2020-01-24
Applicant: Apple Inc.
Inventor： Gregory S. Mathews , Kai Lun Hsiung , Lakshmi Narasimha Murthy Nukala , Peter Fu , Rakesh L. Notani , Sukalpa Biswas , Thejasvi Magudilu Vijayaraj , Yanzhe Liu , Shane J. Keil
IPC: G06F3/06
Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller is configured to transition between read turns and writes turn according to a turn schedule. In some embodiments, the memory controller also receives reports from circuitry requesting memory transactions and determines a current latency tolerance value based on the reports. In some embodiments, the memory controller is configured to switch from a write turn to a read turn prior to a scheduled switch based on the current latency tolerance meeting a threshold value.
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