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公开(公告)号：US11080188B1
公开(公告)日：2021-08-03
申请号：US15939099
申请日：2018-03-28
Applicant: Apple Inc.
Inventor： Jonathan Y. Tong , Ronald P. Hall , Christopher Colletti , David E. Kroesche , James N. Hardage, Jr.
IPC: G06F12/0815 , G06F12/1036 , G06F12/0808 , G06F12/1009
Abstract: A system and method for efficiently handling maintenance requests among multiple processors. In various embodiments, a given processor of multiple processors receives a maintenance request. If maintenance requests are not currently being blocked, then the given processor determines a type of the maintenance request and updates one or more maintenance type counters based on the type. If one or more counters exceed a threshold, an indication is generated specifying maintenance requests received at a later time are to be held. The received maintenance request is processed. Different types of maintenance requests are used for invalidating entries in the instruction cache, for invalidating entries in a TLB and for synchronizing page table updates. Afterward, software applications continue processing. Forward progress of the software applications is measured using one or more metrics. If forward progress has been achieved, then one or more maintenance type counters are reset.
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公开(公告)号：US09928115B2
公开(公告)日：2018-03-27
申请号：US14844212
申请日：2015-09-03
Applicant: Apple Inc.
Inventor： James N. Hardage, Jr. , Daniel U. Becker , Christopher M. Tsay , Richard F. Russo , Shih-Chieh R. Wen , Richard H. Larson
IPC: G06F9/50 , G06F12/084 , G06F9/30 , G06F9/38 , G06F12/0813
CPC classification number: G06F9/5088 , G06F9/30101 , G06F9/3828 , G06F12/0813 , G06F12/084 , G06F2212/1028 , G06F2212/314 , Y02D10/13
Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. The processor may support multiple processor states (PStates). Each PState may specify an operating point (e.g. a combination of supply voltage magnitude and clock frequency), and each PState may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core. The context switch may be performed using a special purpose register (SPR) interconnect. Each processor core in a given processor may be coupled to the SPR interconnect to permit access to the external SPRs.
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Patent Agency Ranking
公开(公告)号：US11422821B1
公开(公告)日：2022-08-23
申请号：US16120675
申请日：2018-09-04
Applicant: Apple Inc.
Inventor： James N. Hardage, Jr. , Christopher M. Tsay , Mahesh K. Reddy
Abstract: A system and method for efficiently handling instruction execution ordering. In various embodiments, a processor includes multiple execution lanes, each executing instructions of a particular type, which are not executed by one or more of the other execution lanes. The instruction queue includes one queue for each particular execution lane. Control logic identifies a current youngest age used in allocated entries of the multiple queues, and determines a starting age based on the identified current youngest age and the number of instructions to be issued. Beginning with the determined starting age, ages (in program order) are assigned to a group of instructions being allocated in the multiple queues. Ages of entries in the multiple queues are updated for instructions not being issued based on the number of instructions being issued. Instructions being issued have age differences between them below a threshold.
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4.发明申请Processor Including Multiple Dissimilar Processor Cores that Implement Different Portions of Instruction Set Architecture 有权处理器包括实现不同部分的指令集架构的多个不相似的处理器内核公开(公告)号：US20160147290A1
公开(公告)日：2016-05-26
申请号：US14548912
申请日：2014-11-20
Applicant: Apple Inc.
IPC: G06F1/32
CPC classification number: G06F1/3293 , G06F1/3275 , G06F1/3287 , G06F9/5094 , Y02D10/122 , Y02D10/171
Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance, but may be optimized for efficiency. Additionally, in some embodiments, some features of the instruction set architecture implemented by the processor may be implemented in only one of the cores that make up the processor. If such a feature is invoked by a code sequence while a different core is active, the processor may swap cores to the core the implements the feature. Alternatively, an exception may be taken and an exception handler may be executed to identify the feature and activate the corresponding core.
Abstract translation: 在一个实施例中，集成电路可以包括一个或多个处理器。 每个处理器可以包括多个处理器核心，并且每个核心具有不同的设计/实现和性能水平。 例如，可以实现用于高性能的核心，并且可以以较低的最大性能来实现另一个核心，但是可以针对效率进行优化。 另外，在一些实施例中，由处理器实现的指令集架构的一些特征可以仅在构成处理器的一个核中实现。 如果在不同核心处于活动状态时由代码序列调用这样的特征，则处理器可以将核心交换到核心来实现该特征。 或者，可以采取异常并且可以执行异常处理程序来识别特征并激活相应的核。
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公开(公告)号：US10401945B2
公开(公告)日：2019-09-03
申请号：US15935274
申请日：2018-03-26
Applicant: Apple Inc.
IPC: G06F1/32 , G06F1/3293 , G06F1/3234 , G06F1/3287 , G06F9/50
Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance, but may be optimized for efficiency. Additionally, in some embodiments, some features of the instruction set architecture implemented by the processor may be implemented in only one of the cores that make up the processor. If such a feature is invoked by a code sequence while a different core is active, the processor may swap cores to the core the implements the feature. Alternatively, an exception may be taken and an exception handler may be executed to identify the feature and activate the corresponding core.
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公开(公告)号：US10372500B1
公开(公告)日：2019-08-06
申请号：US15046364
申请日：2016-02-17
Applicant: Apple Inc.
Inventor： Christopher S. Thomas , James N. Hardage, Jr. , Christopher M. Tsay
Abstract: In some embodiments, a system includes a register file, a plurality of clock gating circuits, a free list circuit, and a register allocation adjustment circuit. The register file includes a plurality of registers. The clock gating circuits control receipt of a clock signal at respective regions of registers. The free list circuit performs multiple search operations in parallel to identify unallocated registers. The register allocation adjustment circuit implements a mapping between registers identified by the free list circuit and registers of the register file such that the multiple search operations identify whether registers of a first region are unallocated prior to identifying whether registers of a second region are unallocated. As a result, a region of the register file is less likely to be in use during a particular clock cycle and a clock gating circuit may prevent a clock signal from being received at the region.
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公开(公告)号：US09958932B2
公开(公告)日：2018-05-01
申请号：US14548912
申请日：2014-11-20
Applicant: Apple Inc.
CPC classification number: G06F1/3293 , G06F1/3275 , G06F1/3287 , G06F9/5094 , Y02D10/122 , Y02D10/171
Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance, but may be optimized for efficiency. Additionally, in some embodiments, some features of the instruction set architecture implemented by the processor may be implemented in only one of the cores that make up the processor. If such a feature is invoked by a code sequence while a different core is active, the processor may swap cores to the core the implements the feature. Alternatively, an exception may be taken and an exception handler may be executed to identify the feature and activate the corresponding core.
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