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公开(公告)号：US20170068575A1
公开(公告)日：2017-03-09
申请号：US14844212
申请日：2015-09-03
Applicant: Apple Inc.
Inventor： James N. Hardage, JR. , Daniel U. Becker , Christopher M. Tsay , Richard F. Russo , Shih-Chieh R. Wen , Richard H. Larson
CPC classification number: G06F9/5088 , G06F9/30101 , G06F9/3828 , G06F12/0813 , G06F12/084 , G06F2212/1028 , G06F2212/314 , Y02D10/13
Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. The processor may support multiple processor states (PStates). Each PState may specify an operating point (e.g. a combination of supply voltage magnitude and clock frequency), and each PState may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core. The context switch may be performed using a special purpose register (SPR) interconnect. Each processor core in a given processor may be coupled to the SPR interconnect to permit access to the external SPRs.
Abstract translation: 在一个实施例中，集成电路可以包括一个或多个处理器。 每个处理器可以包括多个处理器核心，并且每个核心具有不同的设计/实现和性能水平。 处理器可以支持多种处理器状态（PState）。 每个PState可以指定工作点（例如，电源电压幅度和时钟频率的组合），并且每个PState可以映射到处理器核心之一。 在运行期间，其中一个核心是活动的：当前PState映射到的核心。 如果选择新的PState并将其映射到不同的核心，则处理器可以自动地将处理器状态切换到新选择的核心，并且可以在该核心上开始执行。 可以使用专用寄存器（SPR）互连来执行上下文切换。 给定处理器中的每个处理器核心可以耦合到SPR互连以允许访问外部SPR。
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公开(公告)号：US20220083484A1
公开(公告)日：2022-03-17
申请号：US17246311
申请日：2021-04-30
Applicant: Apple Inc.
Inventor： Jeffrey E. Gonion , Charles E. Tucker , Tal Kuzi , Richard F. Russo , Mridul Agarwal , Christopher M. Tsay , Gideon N. Levinsky , Shih-Chieh Wen
Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.
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公开(公告)号：US10372500B1
公开(公告)日：2019-08-06
申请号：US15046364
申请日：2016-02-17
Applicant: Apple Inc.
Inventor： Christopher S. Thomas , James N. Hardage, Jr. , Christopher M. Tsay
Abstract: In some embodiments, a system includes a register file, a plurality of clock gating circuits, a free list circuit, and a register allocation adjustment circuit. The register file includes a plurality of registers. The clock gating circuits control receipt of a clock signal at respective regions of registers. The free list circuit performs multiple search operations in parallel to identify unallocated registers. The register allocation adjustment circuit implements a mapping between registers identified by the free list circuit and registers of the register file such that the multiple search operations identify whether registers of a first region are unallocated prior to identifying whether registers of a second region are unallocated. As a result, a region of the register file is less likely to be in use during a particular clock cycle and a clock gating circuit may prevent a clock signal from being received at the region.
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公开(公告)号：US20240311319A1
公开(公告)日：2024-09-19
申请号：US18674203
申请日：2024-05-24
Applicant: Apple Inc.
Inventor： Jeffrey E. Gonion , Charles E. Tucker , Tal Kuzi , Richard F. Russo , Mridul Agarwal , Christopher M. Tsay , Gideon N. Levinsky , Shih-Chieh Wen , Lior Zimet
Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.
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公开(公告)号：US20220083338A1
公开(公告)日：2022-03-17
申请号：US17469504
申请日：2021-09-08
Applicant: Apple Inc.
Inventor： Jeff Gonion , John H. Kelm , James Vash , Pradeep Kanapathipillai , Mridul Agarwal , Gideon N. Levinsky , Richard F. Russo , Christopher M. Tsay
IPC: G06F9/30 , G06F12/0875 , G06F12/02
Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.
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Patent Agency Ranking
公开(公告)号：US09928115B2
公开(公告)日：2018-03-27
申请号：US14844212
申请日：2015-09-03
Applicant: Apple Inc.
Inventor： James N. Hardage, Jr. , Daniel U. Becker , Christopher M. Tsay , Richard F. Russo , Shih-Chieh R. Wen , Richard H. Larson
IPC: G06F9/50 , G06F12/084 , G06F9/30 , G06F9/38 , G06F12/0813
CPC classification number: G06F9/5088 , G06F9/30101 , G06F9/3828 , G06F12/0813 , G06F12/084 , G06F2212/1028 , G06F2212/314 , Y02D10/13
Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. The processor may support multiple processor states (PStates). Each PState may specify an operating point (e.g. a combination of supply voltage magnitude and clock frequency), and each PState may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core. The context switch may be performed using a special purpose register (SPR) interconnect. Each processor core in a given processor may be coupled to the SPR interconnect to permit access to the external SPRs.
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公开(公告)号：US12007920B2
公开(公告)日：2024-06-11
申请号：US18301837
申请日：2023-04-17
Applicant: Apple Inc.
Inventor： Jeffrey E. Gonion , Charles E. Tucker , Tal Kuzi , Richard F. Russo , Mridul Agarwal , Christopher M. Tsay , Gideon N. Levinsky , Shih-Chieh Wen , Lior Zimet
Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.
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公开(公告)号：US20230333851A1
公开(公告)日：2023-10-19
申请号：US18336704
申请日：2023-06-16
Applicant: Apple Inc.
Inventor： Jeff Gonion , John H. Kelm , James Vash , Pradeep Kanapathipillai , Mridul Agarwal , Gideon N. Levinsky , Richard F. Russo , Christopher M. Tsay
IPC: G06F9/30 , G06F12/02 , G06F12/0875 , G06F9/38
CPC classification number: G06F9/30087 , G06F9/30043 , G06F12/0238 , G06F12/0875 , G06F9/30047 , G06F9/3834 , G06F9/30101
Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.
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公开(公告)号：US20230251985A1
公开(公告)日：2023-08-10
申请号：US18301837
申请日：2023-04-17
Applicant: Apple Inc.
Inventor： Jeffrey E. Gonion , Charles E. Tucker , Tal Kuzi , Richard F. Russo , Mridul Agarwal , Christopher M. Tsay , Gideon N. Levinsky , Shih-Chieh Wen , Lior Zimet
Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.
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公开(公告)号：US11720360B2
公开(公告)日：2023-08-08
申请号：US17469504
申请日：2021-09-08
Applicant: Apple Inc.
Inventor： Jeff Gonion , John H. Kelm , James Vash , Pradeep Kanapathipillai , Mridul Agarwal , Gideon N. Levinsky , Richard F. Russo , Christopher M. Tsay
IPC: G06F9/30 , G06F12/02 , G06F12/0875 , G06F9/38
CPC classification number: G06F9/30087 , G06F9/30043 , G06F9/30047 , G06F9/30101 , G06F9/3834 , G06F12/0238 , G06F12/0875
Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.
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