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    Method for reduced power clock frequency monitoring
    2.
    发明授权
    Method for reduced power clock frequency monitoring 有权

    公开(公告)号：US09647653B2

    公开(公告)日：2017-05-09

    申请号：US14730473

    申请日：2015-06-04

    申请人： Apple Inc.

    发明人： Shu-Yi Yu ,  Jean-Didier Allegrucci ,  Timothy Paaske ,  Deniz Balkan

    IPC分类号： H03K5/19 ,  H03K5/26

    CPC分类号： H03K5/19 ,  H03K5/26

    摘要： An apparatus may include first and second clock monitors. The first clock monitor may be configured to receive a first clock signal and assert a first signal if the frequency of the first clock signal is greater than a first upper threshold and assert a second signal if the frequency of the first clock signal is less than a first lower threshold. The second clock monitor may be configured to receive a second clock signal with a frequency higher than that of the first clock signal. The second clock monitor may be configured to compare the second clock signal, dependent upon the first clock signal, to second upper and lower thresholds and assert a third signal if the frequency of the second clock signal is greater than the second upper threshold and assert a fourth signal if the frequency is less than the second lower threshold.

    METHOD FOR REDUCED POWER CLOCK FREQUENCY MONITORING
    4.
    发明申请
    METHOD FOR REDUCED POWER CLOCK FREQUENCY MONITORING 有权
    降低功率时钟频率监测的方法

    公开(公告)号：US20160359476A1

    公开(公告)日：2016-12-08

    申请号：US14730473

    申请日：2015-06-04

    申请人： Apple Inc.

    发明人： Shu-Yi Yu ,  Jean-Didier Allegrucci ,  Timothy Paaske ,  Deniz Balkan

    IPC分类号： H03K5/19 ,  H03K5/26

    CPC分类号： H03K5/19 ,  H03K5/26

    摘要： An apparatus may include first and second clock monitors. The first clock monitor may be configured to receive a first clock signal and assert a first signal if the frequency of the first clock signal is greater than a first upper threshold and assert a second signal if the frequency of the first clock signal is less than a first lower threshold. The second clock monitor may be configured to receive a second clock signal with a frequency higher than that of the first clock signal. The second clock monitor may be configured to compare the second clock signal, dependent upon the first clock signal, to second upper and lower thresholds and assert a third signal if the frequency of the second clock signal is greater than the second upper threshold and assert a fourth signal if the frequency is less than the second lower threshold.

    摘要翻译： 装置可以包括第一和第二时钟监视器。 如果第一时钟信号的频率大于第一上限阈值，则第一时钟监视器可以被配置为接收第一时钟信号并且断言第一信号，并且如果第一时钟信号的频率小于第一时钟信号，则断言第二信号 第一个下限 第二时钟监视器可以被配置为接收频率高于第一时钟信号的频率的第二时钟信号。 第二时钟监视器可被配置为根据第一时钟信号将第二时钟信号与第二上限和下限阈值进行比较，并且如果第二时钟信号的频率大于第二上限阈值则断言第三信号，并且断言第 第四信号，如果频率小于第二较低阈值。

    Precise Time Management Using Local Time Base
    6.
    发明申请
    Precise Time Management Using Local Time Base 有权

    公开(公告)号：US20220085969A1

    公开(公告)日：2022-03-17

    申请号：US17472242

    申请日：2021-09-10

    申请人： Apple Inc.

    发明人： Christopher D. Finan ,  Alexander Ukanwa ,  Charles F. Dominguez ,  Jean-Didier Allegrucci ,  Jeffrey J. Irwin ,  Kalpana Bansal ,  Michael Bekerman ,  Remi Clavel

    IPC分类号： H04L7/00

    摘要： A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.