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9 条记录 (耗时 0.019 秒)

    Decoding Status Flag Techniques for Memory Circuits
    1.
    发明公开
    Decoding Status Flag Techniques for Memory Circuits 审中-公开

    公开(公告)号：US20230325274A1

    公开(公告)日：2023-10-12

    申请号：US18323178

    申请日：2023-05-24

    申请人： Apple Inc.

    发明人： Farid Nemati ,  Steven R. Hutsell ,  Gregory S. Mathews ,  Yi Chun Chen ,  Kevin C. Wong ,  Kalpana Bansal

    IPC分类号： G06F11/07 ,  G06F11/10

    CPC分类号： G06F11/1064 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/106

    摘要： Techniques are disclosed relating to improving memory reliability. In some embodiments, memory circuitry includes memory cells configured to store data, interface circuitry, and on-die error correcting code (ECC) circuitry. The ECC circuitry may check read data from the memory cells for errors and correct detected correctable errors to generate corrected data. The memory circuitry may provide read data to a requesting circuit via the interface circuitry, including one or more sets of corrected data from the on-die ECC circuitry. The memory circuitry may provide a decoding status flag (DSF) via the interface circuitry, including to: set the DSF to a first value in response to no error being detected for a given set of provided read data, set the DSF to a second value in response to a correctable error that was detected and corrected by the on-die ECC circuitry to provide a given set of read data, and set the DSF to a third value in response to an uncorrectable error detected by the on-die ECC circuitry.

    Data Corruption Tracking for Memory Reliability
    3.
    发明公开
    Data Corruption Tracking for Memory Reliability 审中-公开

    公开(公告)号：US20230251930A1

    公开(公告)日：2023-08-10

    申请号：US17804932

    申请日：2022-06-01

    申请人： Apple Inc.

    发明人： Farid Nemati ,  Steven R. Hutsell ,  Gregory S. Mathews ,  Yi Chun Chen ,  Kevin C. Wong ,  Kalpana Bansal

    IPC分类号： G06F11/10 ,  G06F11/07

    CPC分类号： G06F11/1064 ,  G06F11/106 ,  G06F11/076 ,  G06F11/0772

    摘要： Techniques are disclosed relating to improving memory reliability, e.g., in the context of memory circuits with limited reliability features. In some embodiments, memory controller circuitry is configured to communicate with memory circuitry via an interface that supports link error detection. The memory controller circuitry may, based on a corruption indicator, transmit a data and parity combination for the first data block that causes the memory circuitry to detect an uncorrectable write interface error. Subsequent reads of the location may therefore cause an uncorrectable error indication. This may advantageously allow the memory controller circuitry to propagate a corruption indicator as an uncorrectable error in the memory circuit, without requiring additional tracking of the indicator by the memory circuit or memory controller, in some embodiments.

    Precise Time Management for Peripheral Device Using Local Time Base
    5.
    发明申请
    Precise Time Management for Peripheral Device Using Local Time Base 有权

    公开(公告)号：US20230091434A1

    公开(公告)日：2023-03-23

    申请号：US17482178

    申请日：2021-09-22

    申请人： Apple Inc.

    发明人： Christopher D. Finan ,  Alexander Ukanwa ,  Charles F. Dominguez ,  Kalpana Bansal ,  Michael Bekerman ,  Remi Clavel

    IPC分类号： G06F1/06 ,  G06F13/42

    摘要： An apparatus for time management of a peripheral device is disclosed. A peripheral interface circuit receives information from a host circuit over a peripheral bus, the host circuit maintaining a global timebase in accordance with a first clock signal within a first clock domain. The peripheral interface circuit maintains, based om a second clock signal within a second clock domain, a first local timebase correlated to the global timebase. A peripheral control circuit operates in a third clock domain and maintains a second local timebase based on the first. The peripheral interface circuit determines phase and frequency differences between the second and third clock signals in determining a correlation between the second and first local timebases. A peripheral logic circuit in the third clock domain performs, operations that utilize a timestamp from the second local timebase, which accounts for correlation with the first local timebase.

    Data corruption tracking for memory reliability
    7.
    发明授权
    Data corruption tracking for memory reliability 有权

    公开(公告)号：US11829242B2

    公开(公告)日：2023-11-28

    申请号：US17804932

    申请日：2022-06-01

    申请人： Apple Inc.

    发明人： Farid Nemati ,  Steven R. Hutsell ,  Gregory S. Mathews ,  Yi Chun Chen ,  Kevin C. Wong ,  Kalpana Bansal

    IPC分类号： G06F11/10 ,  G06F11/07

    CPC分类号： G06F11/1064 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/106

    摘要： Techniques are disclosed relating to improving memory reliability, e.g., in the context of memory circuits with limited reliability features. In some embodiments, memory controller circuitry is configured to communicate with memory circuitry via an interface that supports link error detection. The memory controller circuitry may, based on a corruption indicator, transmit a data and parity combination for the first data block that causes the memory circuitry to detect an uncorrectable write interface error. Subsequent reads of the location may therefore cause an uncorrectable error indication. This may advantageously allow the memory controller circuitry to propagate a corruption indicator as an uncorrectable error in the memory circuit, without requiring additional tracking of the indicator by the memory circuit or memory controller, in some embodiments.

    Precise time management for peripheral device using local time base
    8.
    发明授权
    Precise time management for peripheral device using local time base 有权

    公开(公告)号：US11687115B2

    公开(公告)日：2023-06-27

    申请号：US17482178

    申请日：2021-09-22

    申请人： Apple Inc.

    发明人： Christopher D. Finan ,  Alexander Ukanwa ,  Charles F. Dominguez ,  Kalpana Bansal ,  Michael Bekerman ,  Remi Clavel

    IPC分类号： G06F1/06 ,  G06F13/42

    CPC分类号： G06F1/06 ,  G06F13/423

    摘要： An apparatus for time management of a peripheral device is disclosed. A peripheral interface circuit receives information from a host circuit over a peripheral bus, the host circuit maintaining a global timebase in accordance with a first clock signal within a first clock domain. The peripheral interface circuit maintains, based om a second clock signal within a second clock domain, a first local timebase correlated to the global timebase. A peripheral control circuit operates in a third clock domain and maintains a second local timebase based on the first. The peripheral interface circuit determines phase and frequency differences between the second and third clock signals in determining a correlation between the second and first local timebases. A peripheral logic circuit in the third clock domain performs, operations that utilize a timestamp from the second local timebase, which accounts for correlation with the first local timebase.

    Precise Time Management Using Local Time Base
    9.
    发明申请
    Precise Time Management Using Local Time Base 有权

    公开(公告)号：US20220085969A1

    公开(公告)日：2022-03-17

    申请号：US17472242

    申请日：2021-09-10

    申请人： Apple Inc.

    发明人： Christopher D. Finan ,  Alexander Ukanwa ,  Charles F. Dominguez ,  Jean-Didier Allegrucci ,  Jeffrey J. Irwin ,  Kalpana Bansal ,  Michael Bekerman ,  Remi Clavel

    IPC分类号： H04L7/00

    摘要： A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.