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公开(公告)号：US20230353339A1
公开(公告)日：2023-11-02
申请号：US18311129
申请日：2023-05-02
Applicant: Apple Inc.
Inventor： Christopher D. Finan , Alexander Ukanwa , Charles F. Dominguez , Jean-Didier Allegrucci , Jeffrey J. Irwin , Kalpana Bansal , Michael Bekerman , Remi Clavel
CPC classification number: H04L7/0016 , H04L7/0008 , G06F1/12
Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.
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公开(公告)号：US12028437B2
公开(公告)日：2024-07-02
申请号：US18311129
申请日：2023-05-02
Applicant: Apple Inc.
Inventor： Christopher D. Finan , Alexander Ukanwa , Charles F. Dominguez , Jean-Didier Allegrucci , Jeffrey J. Irwin , Kalpana Bansal , Michael Bekerman , Remi Clavel
CPC classification number: H04L7/0016 , G06F1/12 , H04L7/0008
Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.
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Patent Agency Ranking
公开(公告)号：US11687115B2
公开(公告)日：2023-06-27
申请号：US17482178
申请日：2021-09-22
Applicant: Apple Inc.
Inventor： Christopher D. Finan , Alexander Ukanwa , Charles F. Dominguez , Kalpana Bansal , Michael Bekerman , Remi Clavel
CPC classification number: G06F1/06 , G06F13/423
Abstract: An apparatus for time management of a peripheral device is disclosed. A peripheral interface circuit receives information from a host circuit over a peripheral bus, the host circuit maintaining a global timebase in accordance with a first clock signal within a first clock domain. The peripheral interface circuit maintains, based om a second clock signal within a second clock domain, a first local timebase correlated to the global timebase. A peripheral control circuit operates in a third clock domain and maintains a second local timebase based on the first. The peripheral interface circuit determines phase and frequency differences between the second and third clock signals in determining a correlation between the second and first local timebases. A peripheral logic circuit in the third clock domain performs, operations that utilize a timestamp from the second local timebase, which accounts for correlation with the first local timebase.
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公开(公告)号：US20220085969A1
公开(公告)日：2022-03-17
申请号：US17472242
申请日：2021-09-10
Applicant: Apple Inc.
Inventor： Christopher D. Finan , Alexander Ukanwa , Charles F. Dominguez , Jean-Didier Allegrucci , Jeffrey J. Irwin , Kalpana Bansal , Michael Bekerman , Remi Clavel
IPC: H04L7/00
Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.
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公开(公告)号：US20240372692A1
公开(公告)日：2024-11-07
申请号：US18676210
申请日：2024-05-28
Applicant: Apple Inc.
Inventor： Christopher D. Finan , Alexander Ukanwa , Charles F. Dominguez , Jean-Didier Allegrucci , Jeffrey J. Irwin , Kalpana Bansal , Michael Bekerman , Remi Clavel
Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.
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公开(公告)号：US11683149B2
公开(公告)日：2023-06-20
申请号：US17472242
申请日：2021-09-10
Applicant: Apple Inc.
Inventor： Christopher D. Finan , Alexander Ukanwa , Charles F. Dominguez , Jean-Didier Allegrucci , Jeffrey J. Irwin , Kalpana Bansal , Michael Bekerman , Remi Clavel
CPC classification number: H04L7/0016 , G06F1/12 , H04L7/0008
Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.
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公开(公告)号：US20230091434A1
公开(公告)日：2023-03-23
申请号：US17482178
申请日：2021-09-22
Applicant: Apple Inc.
Inventor： Christopher D. Finan , Alexander Ukanwa , Charles F. Dominguez , Kalpana Bansal , Michael Bekerman , Remi Clavel
Abstract: An apparatus for time management of a peripheral device is disclosed. A peripheral interface circuit receives information from a host circuit over a peripheral bus, the host circuit maintaining a global timebase in accordance with a first clock signal within a first clock domain. The peripheral interface circuit maintains, based om a second clock signal within a second clock domain, a first local timebase correlated to the global timebase. A peripheral control circuit operates in a third clock domain and maintains a second local timebase based on the first. The peripheral interface circuit determines phase and frequency differences between the second and third clock signals in determining a correlation between the second and first local timebases. A peripheral logic circuit in the third clock domain performs, operations that utilize a timestamp from the second local timebase, which accounts for correlation with the first local timebase.
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