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公开(公告)号：US20250104790A1
公开(公告)日：2025-03-27
申请号：US18525088
申请日：2023-11-30
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Jingkui Zheng , Srinivasa Rao Masanam
Abstract: An apparatus for performing memory calibrations during a performance state change is disclosed. A memory controller is configured to convey a clock signal to a memory and includes a calibration control circuit configured to perform a plurality of calibrations of the clock signal during a change from a first one to a second one of a plurality of performance states, and a delay circuit configured to apply a delay to clock signal conveyed to the memory. In performing a one of the calibrations, the calibration control circuit is configured to convey, to the memory, a first command to begin a timing test that generates a count value indicative of a current voltage of the memory, receive the count value from the memory at a conclusion of the timing test, and cause the delay circuit to adjust, based on the count value, the delay applied to the clock signal.
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Patent Agency Ranking
公开(公告)号：US20240211151A1
公开(公告)日：2024-06-27
申请号：US18596046
申请日：2024-03-05
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Jingkui Zheng , David A. Knopf , Satish B. Dulam , Kai Lun Hsiung , Venkata Ramana Malladi , Rahul Ranjan
CPC classification number: G06F3/0632 , G06F3/0614 , G06F3/0658 , G06F3/0673 , G11C7/22 , G11C2207/2254
Abstract: An apparatus for performing a write data strobe concurrent with a reference voltage calibration is disclosed. A memory controller circuit is configured to convey a write clock signal to a memory. The memory controller circuit includes a calibration circuit configured to send a first command to memory to initiate a calibration of the write clock signal and, after an amount of time has elapsed, receive a calibration value from the memory. The memory controller further includes a delay circuit configured to apply a delay to the write clock signal, wherein the calibration circuit is configured to complete calibration of the write clock signal by adjusting the delay applied to the write clock signal in accordance with the calibration value. The calibration circuit is further configured to perform a reference voltage calibration concurrent with the calibration of the write clock signal.
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公开(公告)号：US11960739B1
公开(公告)日：2024-04-16
申请号：US17929191
申请日：2022-09-01
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Jingkui Zheng , David A. Knopf , Satish B. Dulam , Kai Lun Hsiung , Venkata Ramana Malladi , Rahul Ranjan
CPC classification number: G06F3/0632 , G06F3/0614 , G06F3/0658 , G06F3/0673 , G11C7/22 , G11C2207/2254
Abstract: The present disclosure is directed to a reference voltage calibration. An apparatus includes a memory and a memory controller including a calibration circuit configured to perform a reference voltage calibration to determine a reference voltage used to distinguish between logic values read from the memory. The reference voltage calibration comprises performing horizontal calibrations at different reference voltage values to determine a range of delay values applied to a data strobe signal at which valid data is read from the memory. The calibration includes determining scores corresponding to ones of the plurality of horizontal calibrations in which a score for a particular one of the plurality of horizontal calibrations is based on a corresponding range of delay values and a reference voltage margin. Thereafter, the calibration circuit selects a calibrated reference voltage based on the scores corresponding to ones of the plurality of horizontal calibrations.
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公开(公告)号：US20240078029A1
公开(公告)日：2024-03-07
申请号：US17929212
申请日：2022-09-01
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Jingkui Zheng , Ritesh J. Shah , Veera Chockalingam , Naveen Kumar Korada
IPC: G06F3/06 , G11C11/4076 , G11C11/4096
CPC classification number: G06F3/0632 , G06F3/0614 , G06F3/0658 , G06F3/0673 , G11C11/4076 , G11C11/4096
Abstract: Memory calibration with a margin check is disclosed. A memory subsystem includes a memory and a memory controller coupled to the memory. The memory controller includes a calibration circuit configured to perform, during an initialization process, horizontal memory calibrations for ones of a plurality of performance states and to determine and store, in a storage circuit, information indicative of a set of differences between calibration results for pairs of the plurality of performance states. The memory controller is further configured to, subsequent to the initialization process and in response to a change from a first one of the plurality of performance states to a second one of the plurality of performance states set initial memory parameters for the second performance state based on the set of differences. Thereafter, operation begins in the second performance state without performing an initial horizontal calibration.
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公开(公告)号：US20240295976A1
公开(公告)日：2024-09-05
申请号：US18658740
申请日：2024-05-08
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Jingkui Zheng , Ritesh J. Shah , Veera Chockalingam , Naveen Kumar Korada
IPC: G06F3/06 , G11C11/4076 , G11C11/4096 , G11C29/50
CPC classification number: G06F3/0632 , G06F3/0614 , G06F3/0658 , G06F3/0673 , G11C11/4076 , G11C11/4096 , G11C29/50
Abstract: Memory calibration with a margin check is disclosed. A memory subsystem includes a memory and a memory controller coupled to the memory. The memory controller includes a calibration circuit configured to perform, during an initialization process, horizontal memory calibrations for ones of a plurality of performance states and to determine and store, in a storage circuit, information indicative of a set of differences between calibration results for pairs of the plurality of performance states. The memory controller is further configured to, subsequent to the initialization process and in response to a change from a first one of the plurality of performance states to a second one of the plurality of performance states set initial memory parameters for the second performance state based on the set of differences. Thereafter, operation begins in the second performance state without performing an initial horizontal calibration.
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公开(公告)号：US12014060B2
公开(公告)日：2024-06-18
申请号：US17929212
申请日：2022-09-01
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Jingkui Zheng , Ritesh J. Shah , Veera Chockalingam , Naveen Kumar Korada
IPC: G11C29/00 , G06F3/06 , G11C11/4076 , G11C11/4096 , G11C29/50
CPC classification number: G06F3/0632 , G06F3/0614 , G06F3/0658 , G06F3/0673 , G11C11/4076 , G11C11/4096 , G11C29/50
Abstract: Memory calibration with a margin check is disclosed. A memory subsystem includes a memory and a memory controller coupled to the memory. The memory controller includes a calibration circuit configured to perform, during an initialization process, horizontal memory calibrations for ones of a plurality of performance states and to determine and store, in a storage circuit, information indicative of a set of differences between calibration results for pairs of the plurality of performance states. The memory controller is further configured to, subsequent to the initialization process and in response to a change from a first one of the plurality of performance states to a second one of the plurality of performance states set initial memory parameters for the second performance state based on the set of differences. Thereafter, operation begins in the second performance state without performing an initial horizontal calibration.
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