Gain reduction techniques for radio-frequency amplifiers

    公开(公告)号:US12199576B2

    公开(公告)日:2025-01-14

    申请号:US17580128

    申请日:2022-01-20

    Applicant: Apple Inc.

    Abstract: An electronic device may include wireless circuitry with a processor, a transceiver, an antenna, and a front-end module coupled between the transceiver and the antenna. The front-end module may include one or more radio-frequency amplifiers for amplifying a radio-frequency signal. The radio-frequency amplifier may include input transistors cross-coupled with capacitance neutralization transistors and/or coupled to cascode transistors. One or more n-type gain adjustment transistors may be coupled to source terminals of the capacitance neutralization transistors. One or more p-type gain adjustment transistors may be coupled to source terminals of the cascode transistors. One or more processors in the electronic device can selectively activate one or more of the gain adjustment transistors to reduce the gain of the radio-frequency amplifier without degrading noise performance and without altering the in-band frequency response of the radio-frequency amplifier.

    Gain Reduction Techniques for Radio-frequency Amplifiers

    公开(公告)号:US20250105802A1

    公开(公告)日:2025-03-27

    申请号:US18975084

    申请日:2024-12-10

    Applicant: Apple Inc.

    Abstract: An electronic device may include wireless circuitry with a processor, a transceiver, an antenna, and a front-end module coupled between the transceiver and the antenna. The front-end module may include one or more radio-frequency amplifiers for amplifying a radio-frequency signal. The radio-frequency amplifier may include input transistors cross-coupled with capacitance neutralization transistors and/or coupled to cascode transistors. One or more n-type gain adjustment transistors may be coupled to source terminals of the capacitance neutralization transistors. One or more p-type gain adjustment transistors may be coupled to source terminals of the cascode transistors. One or more processors in the electronic device can selectively activate one or more of the gain adjustment transistors to reduce the gain of the radio-frequency amplifier without degrading noise performance and without altering the in-band frequency response of the radio-frequency amplifier.

    Bias Point Selection Circuitry for Improved Linearity

    公开(公告)号:US20250096836A1

    公开(公告)日:2025-03-20

    申请号:US18672960

    申请日:2024-05-23

    Applicant: Apple Inc.

    Abstract: Wireless circuitry is provided that includes a radio-frequency circuit having an input transistor and bias point selection circuitry configured to determine an optimal bias voltage for the input transistor. The bias point selection circuitry may include a replica transistor, a voltage generator configured to output one or more voltage levels to a gate terminal of the replica transistor, a current-to-voltage converter coupled to a source-drain terminal of the replica transistor, an analog-to-digital converter configured to receive analog voltages from the current-to-voltage converter and to output corresponding digital codes based on the received analog voltages, and associated control circuitry configured to receive the digital codes from the analog-to-digital converter and to adjust the voltage generator to output the optimal bias voltage based on the digital codes. The optimal bias voltage produces a third order transconductance of zero for the input transistor, which results in improved linearity for the radio-frequency circuit.

    Electronic Devices with Leakage Cancellation for Range Detection

    公开(公告)号:US20230296751A1

    公开(公告)日:2023-09-21

    申请号:US18068990

    申请日:2022-12-20

    Applicant: Apple Inc.

    CPC classification number: G01S13/36 G01S7/354 H01Q3/36 G01S7/356

    Abstract: An electronic device may include wireless circuitry with a transmit antenna and a receive antenna. Signal bursts may be transmitted by the transmit antenna. A phase shifter may be toggled between a first state that applies a first phase shift and a second state that applies a second phase shift to the signal bursts. The second phase shift may be approximately 180 degrees out-of-phase with the first phase shift. A receive path may receive first reflected signals while the phase shifter is in the first state and second reflected signals while in the second state. The first and second reflected signals may be used to cancel the effects of on-chip leakage or DC offset to recover a signal-of-interest associated with reflection of the signal bursts off an external object. The signal-of-interest may be used to detect a range to the external object.

    Gain Reduction Techniques for Radio-frequency Amplifiers

    公开(公告)号:US20230231522A1

    公开(公告)日:2023-07-20

    申请号:US17580128

    申请日:2022-01-20

    Applicant: Apple Inc.

    Abstract: An electronic device may include wireless circuitry with a processor, a transceiver, an antenna, and a front-end module coupled between the transceiver and the antenna. The front-end module may include one or more radio-frequency amplifiers for amplifying a radio-frequency signal. The radio-frequency amplifier may include input transistors cross-coupled with capacitance neutralization transistors and/or coupled to cascode transistors. One or more n-type gain adjustment transistors may be coupled to source terminals of the capacitance neutralization transistors. One or more p-type gain adjustment transistors may be coupled to source terminals of the cascode transistors. One or more processors in the electronic device can selectively activate one or more of the gain adjustment transistors to reduce the gain of the radio-frequency amplifier without degrading noise performance and without altering the in-band frequency response of the radio-frequency amplifier.

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