公开(公告)号：US20180026613A1

公开(公告)日：2018-01-25

申请号：US15217122

申请日：2016-07-22

Applicant: Apple Inc.

Inventor： Victor Zyuban ,  Norman Rohrer ,  Nimish Kabe ,  Neela Lohith Penmetsa

IPC: H03K5/05 ,  H03K3/037 ,  H03K19/21

CPC classification number: H03K5/05 ,  H03K3/037 ,  H03K5/131 ,  H03K19/0016 ,  H03K19/21

Abstract: Techniques are disclosed relating to dual-edge triggered (DET) clock gater circuitry. In some embodiments, an apparatus includes a first series of DET clock gater circuits configured, when the DET clock gater circuits are not gating an input clock signal, to provide an output clock signal to sequential circuitry. In some embodiments, ones of the DET clock gater circuits are controlled by respective control signals and are configured to maintain a mode indicator indicating whether or not the DET clock gater circuit is inverting the polarity of its input clock when generating an output clock. In some embodiments, the apparatus also includes a first adjustable delay circuit configured to adjust delay imposed on the output clock signal from the first series of DET clock gater circuits based on the number of DET clock gater circuits in the series that are in a particular mode.

公开(公告)号：US10187045B2

公开(公告)日：2019-01-22

申请号：US15217122

申请日：2016-07-22

Applicant: Apple Inc.

Inventor： Victor Zyuban ,  Norman Rohrer ,  Nimish Kabe ,  Neela Lohith Penmetsa

IPC: H03K5/05 ,  H03K19/21 ,  H03K3/037

Abstract: Techniques are disclosed relating to dual-edge triggered (DET) clock gater circuitry. In some embodiments, an apparatus includes a first series of DET clock gater circuits configured, when the DET clock gater circuits are not gating an input clock signal, to provide an output clock signal to sequential circuitry. In some embodiments, ones of the DET clock gater circuits are controlled by respective control signals and are configured to maintain a mode indicator indicating whether or not the DET clock gater circuit is inverting the polarity of its input clock when generating an output clock. In some embodiments, the apparatus also includes a first adjustable delay circuit configured to adjust delay imposed on the output clock signal from the first series of DET clock gater circuits based on the number of DET clock gater circuits in the series that are in a particular mode.

公开(公告)号：US09929723B2

公开(公告)日：2018-03-27

申请号：US15066809

申请日：2016-03-10

Applicant: Apple Inc.

Inventor： Victor Zyuban ,  Neela Lohith Penmetsa

IPC: H03K3/3562 ,  H03K3/356

CPC classification number: H03K3/35625 ,  H03K3/356173

Abstract: Embodiments of the present disclosure relate to a flip flop circuit that obviates the need of a transmission gate. The flip flop includes a first match multiplexer, a second match multiplexer and a separable inverter. The first match multiplexer receives an input data signal and generates a feedback output based on the input data signal and the logic levels at two nodes coupled to the first match multiplexer. The separable inverter receives the feedback output and switches the logic level of one of two nodes but maintains the logic level per each clock cycle. The second match multiplexer generates a signal output based on the logic levels at the two nodes and the signal output that is fed back into the second match multiplexer. Embodiments may reduce power consumption and operate at lower voltages.

公开(公告)号：US20170264274A1

公开(公告)日：2017-09-14

申请号：US15066809

申请日：2016-03-10

Applicant: Apple Inc.

Inventor： Victor Zyuban ,  Neela Lohith Penmetsa

IPC: H03K3/3562

CPC classification number: H03K3/35625 ,  H03K3/356173

Abstract: Embodiments of the present disclosure relate to a flip flop circuit that obviates the need of a transmission gate. The flip flop includes a first match multiplexer, a second match multiplexer and a separable inverter. The first match multiplexer receives an input data signal and generates a feedback output based on the input data signal and the logic levels at two nodes coupled to the first match multiplexer. The separable inverter receives the feedback output and switches the logic level of one of two nodes but maintains the logic level per each clock cycle. The second match multiplexer generates a signal output based on the logic levels at the two nodes and the signal output that is fed back into the second match multiplexer. Embodiments may reduce power consumption and operate at lower voltages.