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公开(公告)号：US20240134737A1
公开(公告)日：2024-04-25
申请号：US18490675
申请日：2023-10-18
Applicant: Apple Inc.
Inventor： Marc A. Schaub , Roy G. Moss , Michael Bekerman
CPC classification number: G06F11/0793 , G06F13/28
Abstract: Systems, apparatuses, and methods for error detection and recovery when streaming data are described. A system includes one or more companion direct memory access (DMA) subsystems for transferring data. When an error is detected for a component of the companion DMA subsystem(s), the operations performed by the other components need to gracefully adapt to this error so that operations face only a minimal disruption. For example, while one or more consumers are still consuming a first frame, a companion router receives an indication of an error for a second frame, causing the companion router to send a router frame abort message to a route manager. In response, the route manager waits until the consumer(s) are consuming the second frame before sending them a frame abort message. The consumer(s) flush their pipeline and transition to an idle state waiting for a third frame after receiving the frame abort message.
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公开(公告)号：US20180032281A1
公开(公告)日：2018-02-01
申请号：US15225343
申请日：2016-08-01
Applicant: Apple Inc.
Inventor： Manu Gulati , Peter F. Holland , Erik P. Machnicki , Robert E. Jeter , Rakesh L. Notani , Neeraj Parik , Marc A. Schaub
IPC: G06F3/06 , G11C11/406
CPC classification number: G06F3/0656 , G06F3/0604 , G06F3/0683 , G06F13/1673 , G11C11/40615
Abstract: In some embodiments, a system includes a memory system, a real-time computing device, and a controller. The real-time computing device stores data within a local buffer having a corresponding storage threshold, where the data satisfies the storage threshold, and where the storage threshold is based on a latency of the memory system and an expected rate of utilization of the data of the local buffer. The controller detects that the memory system should perform an operation, where the memory system is unavailable to the real-time computing device during the operation. In response to detecting that an amount of time for the operation exceeds an amount of time corresponding to the storage threshold, the controller overrides the storage threshold. The controller may override the storage threshold by modifying the storage threshold and by overriding a default priority for access requests of the real-time computing device to the memory system.
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公开(公告)号：US20150084970A1
公开(公告)日：2015-03-26
申请号：US14037318
申请日：2013-09-25
Applicant: Apple Inc.
Inventor： Marc A. Schaub , Joseph J. Cheng , Mark P. Rygh , Guy Cote
CPC classification number: G06T1/20 , G06T1/60 , H04N19/423 , H04N19/436 , H04N19/61
Abstract: Block processing pipeline methods and apparatus in which pixel data from a reference frame is prefetched into a search window memory. The search window may include two or more overlapping regions of pixels from the reference frame corresponding to blocks from the rows in the input frame that are currently being processed in the pipeline. Thus, the pipeline may process blocks from multiple rows of an input frame using one set of pixel data from a reference frame that is stored in a shared search window memory. The search window may be advanced by one column of blocks by initiating a prefetch for a next column of reference data from a memory. The pipeline may also include a reference data cache that may be used to cache a portion of a reference frame and from which at least a portion of a prefetch for the search window may be satisfied.
Abstract translation: 块处理流水线方法和装置，其中来自参考帧的像素数据被预取到搜索窗口存储器中。 搜索窗口可以包括对应于当前正在流水线处理的输入帧中的行的来自参考帧的两个或更多个重叠区域的像素。 因此，流水线可以使用来自存储在共享搜索窗口存储器中的参考帧的一组像素数据来处理来自输入帧的多行的块。 搜索窗口可以由一列块提前，通过从存储器发起下一列参考数据的预取。 流水线还可以包括可用于缓存参考帧的一部分的参考数据高速缓存，并且可以从该参考数据高速缓冲存储器可以满足搜索窗口的预取的至少一部分。
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公开(公告)号：US10546558B2
公开(公告)日：2020-01-28
申请号：US14262298
申请日：2014-04-25
Applicant: Apple Inc.
Inventor： Marc A. Schaub , Jeffrey J. Irwin , Peter F. Holland
IPC: G09G5/36
Abstract: Systems, apparatuses, and methods for aggregating memory requests with opportunism in a display pipeline. Memory requests are aggregated for each requestor of a plurality of requestors in the display pipeline. When the number of memory requests for a given requestor reaches a corresponding threshold, memory requests may be issued for the given requestor. In response to determining the given requestor has reached its threshold, other requestors may issue memory requests even if they have not yet aggregated enough memory requests to reach their corresponding thresholds.
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5.发明授权Multiple quality of service (QoS) thresholds or clock gating thresholds based on memory stress level 有权基于内存应力水平的多种服务质量（QoS）阈值或时钟门控阈值公开(公告)号：US09019291B2
公开(公告)日：2015-04-28
申请号：US13775641
申请日：2013-02-25
Applicant: Apple Inc.
Inventor： Peter F. Holland , Marc A. Schaub
CPC classification number: G06T1/60
Abstract: In an embodiment, a display control unit is configured to transmit read operations to the memory in the system to read image data for processing, and may employ QoS levels with the read operations to ensure that enough data is provided to satisfy the real time display requirements. To determine which QoS level to use for a given read request, the display control unit may be configured to compare an amount of image data in the display control unit (e.g. in various input and/or output buffers in the display control unit) to one or more thresholds. The display control unit may also be configured to dynamically update the thresholds based on a memory stress level in the memory controller.
Abstract translation: 在一个实施例中，显示控制单元被配置为向系统中的存储器发送读取操作以读取用于处理的图像数据，并且可以利用读取操作的QoS级别来确保提供足够的数据以满足实时显示要求 。 为了确定对于给定的读取请求使用哪个QoS级别，显示控制单元可以被配置为将显示控制单元中的图像数据量（例如，在显示控制单元中的各种输入和/或输出缓冲器中）与一个 或更多阈值。 显示控制单元还可以被配置为基于存储器控制器中的存储器应力水平来动态地更新阈值。
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Patent Agency Ranking
公开(公告)号：US20150084968A1
公开(公告)日：2015-03-26
申请号：US14037313
申请日：2013-09-25
Applicant: Apple Inc.
Inventor： Joseph J. Cheng , Guy Cote , Marc A. Schaub , Jim C. Chou
CPC classification number: G06T1/20 , G06T1/60 , H04N19/423 , H04N19/436 , H04N19/61
Abstract: Methods and apparatus for caching neighbor data in a block processing pipeline that processes blocks in knight's order with quadrow constraints. Stages of the pipeline may maintain two local buffers that contain data from neighbor blocks of a current block. A first buffer contains data from the last C blocks processed at the stage. A second buffer contains data from neighbor blocks on the last row of a previous quadrow. Data for blocks on the bottom row of a quadrow are stored to an external memory at the end of the pipeline. When a block on the top row of a quadrow is input to the pipeline, neighbor data from the bottom row of the previous quadrow is read from the external memory and passed down the pipeline, each stage storing the data in its second buffer and using the neighbor data in the second buffer when processing the block.
Abstract translation: 用于在块处理管道中缓存邻居数据的方法和装置，其以四限制约束以骑士顺序处理块。 管道的阶段可以维护两个包含当前块的相邻块的数据的本地缓冲器。 第一个缓冲区包含在该阶段处理的最后一个C块的数据。 第二个缓冲区包含来自前一个四边形最后一行的相邻块的数据。 四边形底行中的块的数据存储在流水线末端的外部存储器中。 当四边形的顶行上的块被输入到流水线时，从外部存储器读取来自前一个四边形的底行的邻居数据，并将其传送到流水线，每个级将数据存储在其第二缓冲器中，并使用 处理块时第二个缓冲区中的邻居数据。
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7.发明申请Multiple Quality of Service (QoS) Thresholds or Clock Gating Thresholds Based on Memory Stress Level 有权基于内存应力水平的多种服务质量（QoS）阈值或时钟门控阈值公开(公告)号：US20140240332A1
公开(公告)日：2014-08-28
申请号：US13775641
申请日：2013-02-25
Applicant: APPLE INC.
Inventor： Peter F. Holland , Marc A. Schaub
IPC: G06T1/60
CPC classification number: G06T1/60
Abstract: In an embodiment, a display control unit is configured to transmit read operations to the memory in the system to read image data for processing, and may employ QoS levels with the read operations to ensure that enough data is provided to satisfy the real time display requirements. To determine which QoS level to use for a given read request, the display control unit may be configured to compare an amount of image data in the display control unit (e.g. in various input and/or output buffers in the display control unit) to one or more thresholds. The display control unit may also be configured to dynamically update the thresholds based on a memory stress level in the memory controller.
Abstract translation: 在一个实施例中，显示控制单元被配置为向系统中的存储器发送读取操作以读取用于处理的图像数据，并且可以采用具有读取操作的QoS等级来确保提供足够的数据以满足实时显示要求 。 为了确定对于给定的读取请求使用哪个QoS级别，显示控制单元可以被配置为将显示控制单元中的图像数据量（例如，在显示控制单元中的各种输入和/或输出缓冲器中）与一个 或更多阈值。 显示控制单元还可以被配置为基于存储器控制器中的存储器应力水平来动态地更新阈值。
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公开(公告)号：US20240232000A9
公开(公告)日：2024-07-11
申请号：US18490675
申请日：2023-10-19
Applicant: Apple Inc.
Inventor： Marc A. Schaub , Roy G. Moss , Michael Bekerman
CPC classification number: G06F11/0793 , G06F13/28
Abstract: Systems, apparatuses, and methods for error detection and recovery when streaming data are described. A system includes one or more companion direct memory access (DMA) subsystems for transferring data. When an error is detected for a component of the companion DMA subsystem(s), the operations performed by the other components need to gracefully adapt to this error so that operations face only a minimal disruption. For example, while one or more consumers are still consuming a first frame, a companion router receives an indication of an error for a second frame, causing the companion router to send a router frame abort message to a route manager. In response, the route manager waits until the consumer(s) are consuming the second frame before sending them a frame abort message. The consumer(s) flush their pipeline and transition to an idle state waiting for a third frame after receiving the frame abort message.
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公开(公告)号：US12001365B2
公开(公告)日：2024-06-04
申请号：US16922623
申请日：2020-07-07
Applicant: Apple Inc.
Inventor： Marc A. Schaub , Roy G. Moss
CPC classification number: G06F13/37 , G06F9/30069 , G06F9/5022 , G06F9/544 , G06F13/1642 , G06F13/28
Abstract: Systems, apparatuses, and methods for performing scatter and gather direct memory access (DMA) streaming through a circular buffer are described. A system includes a circular buffer, producer DMA engine, and consumer DMA engine. After the producer DMA engine writes or skips over a given data chunk of a first frame to the buffer, the producer DMA engine sends an updated write pointer to the consumer DMA engine indicating that a data credit has been committed to the buffer and that the data credit is ready to be consumed. After the consumer DMA engine reads or skips over the given data chunk of the first frame from the buffer, the consumer DMA engine sends an updated read pointer to the producer DMA engine indicating that the data credit has been consumed and that space has been freed up in the buffer to be reused by the producer DMA engine.
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公开(公告)号：US20220012201A1
公开(公告)日：2022-01-13
申请号：US16922623
申请日：2020-07-07
Applicant: Apple Inc.
Inventor： Marc A. Schaub , Roy G. Moss
Abstract: Systems, apparatuses, and methods for performing scatter and gather direct memory access (DMA) streaming through a circular buffer are described. A system includes a circular buffer, producer DMA engine, and consumer DMA engine. After the producer DMA engine writes or skips over a given data chunk of a first frame to the buffer, the producer DMA engine sends an updated write pointer to the consumer DMA engine indicating that a data credit has been committed to the buffer and that the data credit is ready to be consumed. After the consumer DMA engine reads or skips over the given data chunk of the first frame from the buffer, the consumer DMA engine sends an updated read pointer to the producer DMA engine indicating that the data credit has been consumed and that space has been freed up in the buffer to be reused by the producer DMA engine.
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