公开(公告)号：US20200350318A1

公开(公告)日：2020-11-05

申请号：US16931154

申请日：2020-07-16

Applicant: Applied Materials, Inc.

Inventor： Arvind KUMAR ,  Mahendra PAKALA ,  Sanjeev MANHAS ,  Satendra Kumar GAUTAM

IPC: H01L27/108 ,  H01L21/28 ,  H01L29/49

Abstract: Embodiments of the present disclosure generally relate to a storage device. More specifically, embodiments described herein generally relate to a dynamic random-access memory and the method of making thereof. In one embodiment, a cell array includes at least an active region and a field region adjacent to the active region. The active region includes at least one trench, a dielectric layer disposed in the trench, a first conformal layer disposed on the dielectric layer, and a conductive material disposed on the first conformal layer. The field region includes a trench, a dielectric layer disposed in the trench, a second conformal layer disposed on the dielectric layer, and a conductive material disposed on the second conformal layer. The second conformal layer has a different composition than the first conformal layer.

公开(公告)号：US20220285362A1

公开(公告)日：2022-09-08

申请号：US17674353

申请日：2022-02-17

Applicant: Applied Materials, Inc.

Inventor： Fredrick David FISHBURN ,  Arvind KUMAR ,  Sony VARGHESE ,  Chang Seok KANG ,  Sung-Kwan KANG ,  Tomohiko KITAJIMA

IPC: H01L27/108 ,  G11C5/10

Abstract: Methods for forming three-dimensional dynamic random-access memory (3D DRAM) structures that leverage a grid pattern of high aspect ratio holes to form subsequent features of the 3D DRAM. The method may include depositing alternating layers of crystalline silicon (c-Si) and crystalline silicon germanium (c-SiGe) using an heteroepitaxy process onto a substrate and HAR etching of a pattern of holes into the substrate. The holes configured to provide chemistry access to laterally etch or deposit materials to form 3D DRAM features without requiring subsequent HAR etching of holes to form the 3D DRAM features.

公开(公告)号：US20240429048A1

公开(公告)日：2024-12-26

申请号：US18745485

申请日：2024-06-17

Applicant: Applied Materials, Inc.

Inventor： Ruiying HAO ,  Thomas KIRSCHENHEITER ,  Arvind KUMAR ,  Mahendra PAKALA ,  Roya BAGHI ,  Balasubramanian PRANATHARTHIHARAN ,  Fredrick FISHBURN

IPC: H01L21/02 ,  H01L29/165

Abstract: A semiconductor device and a method for manufacturing thereof. A substrate is provided. At least one silicon layer is formed on top of the substrate. At least one silicon-germanium layer is formed on top of at least one silicon layer. At least one silicon-germanium layer includes at least one n-type dopant. The semiconductor device having at least one silicon layer and at least one silicon-germanium layer is formed.

公开(公告)号：US20250142911A1

公开(公告)日：2025-05-01

申请号：US18889143

申请日：2024-09-18

Applicant: Applied Materials, Inc.

Inventor： Arvind KUMAR ,  Roya BAGHI ,  Mahendra PAKALA ,  Thomas KIRSCHENHEITER

IPC: H01L29/165 ,  H01L21/02 ,  H01L21/324

Abstract: Embodiments of the present disclosure generally relate to epitaxial film stacks and vapor deposition processes for preparing the epitaxial film stacks. In one or more embodiments, a carbon-doped silicon-germanium and silicon mini-stack is produced with relatively low defects or crystal imperfections. A multi-layered epitaxial stack containing a plurality of the carbon-doped silicon-germanium and silicon mini-stacks is deposited on a substrate. Each multi-layered epitaxial stack contains a carbon-doped silicon germanium stack and a silicon film. The carbon-doped silicon germanium stack contains a carbon-silicon-germanium layer disposed between a first silicon-germanium layer and a second silicon-germanium layer. The silicon film contains the silicon bulk layer disposed on the silicon seed layer. In some embodiments, a method for fabricating the epitaxial film stack includes sequentially depositing a carbon-doped silicon germanium stack and a silicon film to form the carbon-doped silicon-germanium and silicon mini-stack during a deposition cycle.

公开(公告)号：US20220199627A1

公开(公告)日：2022-06-23

申请号：US17551903

申请日：2021-12-15

Applicant: Applied Materials, Inc.

Inventor： Fredrick FISHBURN ,  Arvind KUMAR ,  Sony VARGHESE

IPC: H01L27/108

Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) devices and replacement channel processes for fabricating 3D DRAM devices. In an example, a gate dielectric layer is formed on a sacrificial material, and a gate electrode is formed on the gate dielectric layer. After the gate electrode is formed, the sacrificial material is removed and replaced by a semiconductor material. A channel region of a device (e.g., a transistor) that includes the gate dielectric layer and gate electrode is formed in the semiconductor material. The channel region can be vertical or horizontal with respect to a main surface of a substrate on which the device is formed. A capacitor can be formed, such as before or after the semiconductor material is formed, and is electrically connected to the semiconductor material. The device and the capacitor together can form at least part of a 3D DRAM cell.

公开(公告)号：US20210028282A1

公开(公告)日：2021-01-28

申请号：US16519246

申请日：2019-07-23

Applicant: Applied Materials, Inc.

Inventor： Arvind KUMAR ,  Sanjeev MANHAS ,  Mahendra PAKALA ,  Ellie Y. YIEH

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/04 ,  H01L21/8234

Abstract: The present disclosure provides methods for forming a channel structure in a film stack for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, and a channel structure formed in the film stack, wherein the channel structure is filled with a channel layer and a protective blocking layer, wherein the channel layer has a gradient dopant concentration along a vertical stacking of the film stack.

公开(公告)号：US20200144272A1

公开(公告)日：2020-05-07

申请号：US16243551

申请日：2019-01-09

Applicant: Applied Materials, Inc.

Inventor： Arvind KUMAR ,  Mahendra PAKALA ,  Sanjeev MANHAS ,  Satendra Kumar GAUTAM

IPC: H01L27/108 ,  H01L29/49 ,  H01L21/28

Abstract: Embodiments of the present disclosure generally relate to a storage device. More specifically, embodiments described herein generally relate to a dynamic random-access memory and the method of making thereof. In one embodiment, a cell array includes at least an active region and a field region adjacent to the active region. The active region includes at least one trench, a dielectric layer disposed in the trench, a first conformal layer disposed on the dielectric layer, and a conductive material disposed on the first conformal layer. The field region includes a trench, a dielectric layer disposed in the trench, a second conformal layer disposed on the dielectric layer, and a conductive material disposed on the second conformal layer. The second conformal layer has a different composition than the first conformal layer.