公开(公告)号：US10686033B2

公开(公告)日：2020-06-16

申请号：US16186027

申请日：2018-11-09

Applicant: APPLIED Materials, Inc.

Inventor： Min Gyu Sung ,  Jae Young Lee ,  Johannes Van Meer ,  Sony Varghese ,  Naushad K. Variam

IPC: H01L29/06 ,  H01L21/76 ,  H01L29/417 ,  H01L21/762 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

Abstract: Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include performing a fin cut by removing a first fin section of the plurality of fins and a first portion of the STI material, and forming a second STI material over a second fin section of the plurality of fins, wherein the second fin section is left remaining following removal of the first fin section. The method may further include recessing the STI material and the second STI material, forming a spin-on-carbon (SOC) layer over the semiconductor device, and implanting the STI material and the second STI material through the SOC layer.

公开(公告)号：US20200152519A1

公开(公告)日：2020-05-14

申请号：US16186004

申请日：2018-11-09

Applicant: APPLIED Materials, Inc.

Inventor： Min Gyu Sung ,  Jae Young Lee ,  Johannes Van Meer ,  Sony Varghese ,  Naushad K. Variam

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/10 ,  H01L27/088 ,  H01L21/768

Abstract: Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include recessing the STI material to reveal an upper portion of the plurality of fins, implanting the semiconductor device, and forming a capping layer over the plurality of fins and the STI material. The method may further include removing a first fin section of the plurality of fins and a first portion of the capping layer, wherein a second fin section of the plurality of fins remains following removal of the first fin section.

公开(公告)号：US20240266175A1

公开(公告)日：2024-08-08

申请号：US18105302

申请日：2023-02-03

Applicant: Applied Materials, Inc.

Inventor： Yan Zhang ,  Johannes M. van Meer ,  Jae Young Lee ,  Naushad Variam

IPC: H01L21/265 ,  H01L21/306 ,  H01L21/768

CPC classification number: H01L21/26506 ,  H01L21/30625 ,  H01L21/76898

Abstract: A method of processing a workpiece that will include a backside power delivery network is disclosed. The method includes forming a CMP marker layer in the workpiece at the depth to which the workpiece is to be thinned. This CMP marker layer, which may be a boron-rich layer, serves to slow the chemical-mechanical planarization (CMP) process. To minimize the diffusion of boron in this boron-rich layer, the boron-rich layer is sandwiched by implants of a first species of ions, where this first species of ions serves to slow the diffusion of the boron. In certain embodiments, carbon is used as the first species of ions.

公开(公告)号：US20220068715A1

公开(公告)日：2022-03-03

申请号：US17006428

申请日：2020-08-28

Applicant: Applied Materials, Inc.

Inventor： Andrew Michael Waite ,  Johannes M. van Meer ,  Jae Young Lee

IPC: H01L21/8234 ,  H01L21/26

Abstract: In one embodiment, a method may include providing a substrate, comprising a plurality of surface features, an isolation layer, disposed between the plurality of surface features, and a substrate base, disposed subjacent the isolation layer and the plurality of surface features, wherein the plurality of surface features extend above a surface of the isolation layer. The method may include directing a low energy ion beam to the substrate, when the substrate is heated at a targeted temperature, wherein an altered layer is formed within an outer portion of the isolation layer, and wherein an inner portion of the isolation layer is not implanted.

公开(公告)号：US20210119022A1

公开(公告)日：2021-04-22

申请号：US16660089

申请日：2019-10-22

Applicant: APPLIED Materials, Inc.

Inventor： Jae Young Lee ,  Johannes M. Van Meer ,  Naushad K. Variam

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L29/45 ,  H01L21/225 ,  H01L21/265 ,  H01L21/324 ,  H01L21/285

Abstract: Methods for forming semiconductor devices herein may include providing a metal gate, an interlayer dielectric (ILD), and an etch stop layer over a plurality of fins, wherein the ILD is formed atop the etch stop layer, and wherein the plurality of fins includes a source/drain (S/D) epitaxial region. The method may further include removing the etch stop layer from atop the S/D epitaxial region, and performing, through an opening in the ILD, an ion implant and a dopant ion implant to the S/D epitaxial region. In some embodiments, the method may further include thermally treating the semiconductor device to activate ions of the ion implant or ions of the dopant ion implant in the S/D epitaxial region to form an ultra-shallow junction.

公开(公告)号：US11430898B2

公开(公告)日：2022-08-30

申请号：US16818963

申请日：2020-03-13

Applicant: APPLIED MATERIALS, INC.

Inventor： Jose-Ignacio Del-Agua-Borniquel ,  Hendrik F. W. Dekkers ,  Hans Van Meer ,  Jae Young Lee

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/425 ,  H01L29/24

Abstract: Methods and apparatus for forming a thin film transistor (TFT) having a metal oxide layer. The method may include forming an amorphous metal oxide layer and treating the metal oxide layer with a silicon containing gas or plasma including Si4+ ions. The silicon treatment of the metal oxide layer helps fill the oxygen vacancies in the metal oxide channel layer, leading to a more stable TFT and preventing a negative threshold voltage in the TFT.

公开(公告)号：US11424164B2

公开(公告)日：2022-08-23

申请号：US17006428

申请日：2020-08-28

Applicant: Applied Materials, Inc.

Inventor： Andrew Michael Waite ,  Johannes M. van Meer ,  Jae Young Lee

IPC: H01L21/8234 ,  H01L21/26

Abstract: In one embodiment, a method may include providing a substrate, comprising a plurality of surface features, an isolation layer, disposed between the plurality of surface features, and a substrate base, disposed subjacent the isolation layer and the plurality of surface features, wherein the plurality of surface features extend above a surface of the isolation layer. The method may include directing a low energy ion beam to the substrate, when the substrate is heated at a targeted temperature, wherein an altered layer is formed within an outer portion of the isolation layer, and wherein an inner portion of the isolation layer is not implanted.

公开(公告)号：US20210288186A1

公开(公告)日：2021-09-16

申请号：US16818963

申请日：2020-03-13

Applicant: APPLIED MATERIALS, INC.

Inventor： Jose-Ignacio Del-Agua-Borniquel ,  Hendrik F.W. Dekkers ,  Hans Van Meer ,  Jae Young Lee

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/425 ,  H01L29/24

Abstract: Methods and apparatus for forming a thin film transistor (TFT) having a metal oxide layer. The method may include forming an amorphous metal oxide layer and treating the metal oxide layer with a silicon containing gas or plasma including Si4+ ions. The silicon treatment of the metal oxide layer helps fill the oxygen vacancies in the metal oxide channel layer, leading to a more stable TFT and preventing a negative threshold voltage in the TFT.

公开(公告)号：US10692775B2

公开(公告)日：2020-06-23

申请号：US16186004

申请日：2018-11-09

Applicant: APPLIED Materials, Inc.

Inventor： Min Gyu Sung ,  Jae Young Lee ,  Johannes Van Meer ,  Sony Varghese ,  Naushad K. Variam

IPC: H01L21/82 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/10 ,  H01L27/088 ,  H01L29/78

Abstract: Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include recessing the STI material to reveal an upper portion of the plurality of fins, implanting the semiconductor device, and forming a capping layer over the plurality of fins and the STI material. The method may further include removing a first fin section of the plurality of fins and a first portion of the capping layer, wherein a second fin section of the plurality of fins remains following removal of the first fin section.

公开(公告)号：US20200152735A1

公开(公告)日：2020-05-14

申请号：US16186027

申请日：2018-11-09

Applicant: APPLIED Materials, Inc.

Inventor： Min Gyu Sung ,  Jae Young Lee ,  Johannes Van Meer ,  Sony Varghese ,  Naushad K. Variam

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/762

Abstract: Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include performing a fin cut by removing a first fin section of the plurality of fins and a first portion of the STI material, and forming a second STI material over a second fin section of the plurality of fins, wherein the second fin section is left remaining following removal of the first fin section. The method may further include recessing the STI material and the second STI material, forming a spin-on-carbon (SOC) layer over the semiconductor device, and implanting the STI material and the second STI material through the SOC layer.