公开(公告)号：US20160056050A1

公开(公告)日：2016-02-25

申请号：US14462817

申请日：2014-08-19

Applicant: Applied Materials, Inc.

Inventor： Byungkook KONG ,  Gene LEE ,  Liming YANG

IPC: H01L21/311 ,  H01L27/115

CPC classification number: H01L21/31116 ,  H01J37/32091 ,  H01J37/32146 ,  H01L21/32137 ,  H01L27/11556 ,  H01L27/11582

Abstract: Embodiments of the present disclosure provide methods for forming features in a film stack that may be utilized to form stair-like structures with accurate profiles control in manufacturing three dimensional (3D) stacking of semiconductor chips. In one example, a method of etching a material layer disposed on a substrate using synchronized RF pulses includes providing an etching gas mixture into a processing chamber having a film stack disposed on a substrate, synchronously pulsing a RF source power and a RF bias power into the etching gas mixture at a ratio of less than 0.5, and etching the film stack disposed on the substrate.

Abstract translation: 本公开的实施例提供了用于形成膜堆叠中的特征的方法，其可以用于在制造半导体芯片的三维（3D）堆叠中形成具有精确轮廓控制的阶梯状结构。 在一个示例中，使用同步RF脉冲蚀刻设置在基板上的材料层的方法包括：将蚀刻气体混合物提供到具有设置在基板上的膜堆叠的处理室中，将RF源功率和RF偏置功率同步地脉冲 蚀刻气体混合物的比例小于0.5，并蚀刻设置在基底上的薄膜叠层。