公开(公告)号：US20150064919A1

公开(公告)日：2015-03-05

申请号：US14072430

申请日：2013-11-05

Applicant: APPLIED MATERIALS, INC.

Inventor： Jinsu KIM ,  Xiaosong JI ,  Jinhan CHOI ,  Ho Jeong KIM ,  Byungkook KONG ,  Hoon Sang LEE

IPC: H01L21/3065

CPC classification number: H01L21/3065 ,  H01J37/321 ,  H01J2237/3347 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02315 ,  H01L21/3083 ,  H01L21/31116 ,  H01L21/76224

Abstract: Embodiments of methods for etching a substrate include exposing the substrate to a first plasma formed from an inert gas; exposing the substrate to a second plasma formed from an oxygen-containing gas to form an oxide layer on a bottom and sides of a low aspect ratio feature and a high aspect ratio feature, wherein the oxide layer on the bottom of the low aspect ratio feature is thicker than on the bottom of the high aspect ratio feature; etching the oxide layer from the bottom of the low and high aspect ratio features with a third plasma to expose the bottom of the high aspect ratio feature while the bottom of the low aspect ratio feature remains covered; and exposing the substrate to a fourth plasma formed from a halogen-containing gas to etch the bottom of the low aspect ratio feature and the high aspect ratio feature.

Abstract translation: 用于蚀刻衬底的方法的实施例包括将衬底暴露于由惰性气体形成的第一等离子体; 将衬底暴露于由含氧气体形成的第二等离子体以在低纵横比特征和高纵横比特征的底部和侧面上形成氧化物层，其中低纵横比特征的底部上的氧化物层 比高宽比特征的底部厚; 使用第三等离子体从低和高纵横比特征的底部蚀刻氧化物层，以暴露高纵横比特征的底部，而低纵横比特征的底部保持覆盖; 并将衬底暴露于由含卤素气体形成的第四等离子体，以蚀刻低纵横比特征和高纵横比特征的底部。

公开(公告)号：US20190198338A1

公开(公告)日：2019-06-27

申请号：US15853243

申请日：2017-12-22

Applicant: Applied Materials, Inc.

Inventor： Sang Wook KIM ,  Zhibin WANG ,  Kyoungjin LEE ,  Byungkook KONG

IPC: H01L21/308 ,  H01L21/02 ,  H01L21/311 ,  H01L21/027

Abstract: Embodiments of the present disclosure generally provide a method and apparatus for forming features in a material layer utilizing EUV technologies. In one embodiment, a method of patterning a substrate includes disposing a patterned photoresist layer on a mask layer disposed on a substrate, wherein the patterned photoresist layer has openings with different widths defined in the patterned photoresist layer, forming a compensatory layer along sidewalls of the patterned photoresist layer to modify the widths of the openings and etching the mask layer through the openings with the modified width.

公开(公告)号：US20190371617A1

公开(公告)日：2019-12-05

申请号：US16506520

申请日：2019-07-09

Applicant: Applied Materials, Inc.

Inventor： Chang Wook DOH ,  Zhibin WANG ,  Byungkook KONG ,  Sang Wook KIM ,  Sang-Jun CHOI

IPC: H01L21/3065 ,  H01J37/32

Abstract: Systems and methods discussed herein are directed towards processing of substrates, including forming a plurality of features in a target layer on a substrate. The formation of the plurality of features includes a main etch operation that forms the plurality of features to a first depth in the target layer. The main etch operation is followed by a phase shift sync pulsing (PSSP) operation, and these two operations are repeated iteratively to form the features to a predetermined depth. The PSSP operation includes one or more cycles of RF source power and RF bias power, this cycle deposits a protective coating in and on the features and then etches a portion of the protective coating to expose portions of the feature.

公开(公告)号：US20160056050A1

公开(公告)日：2016-02-25

申请号：US14462817

申请日：2014-08-19

Applicant: Applied Materials, Inc.

Inventor： Byungkook KONG ,  Gene LEE ,  Liming YANG

IPC: H01L21/311 ,  H01L27/115

CPC classification number: H01L21/31116 ,  H01J37/32091 ,  H01J37/32146 ,  H01L21/32137 ,  H01L27/11556 ,  H01L27/11582

Abstract: Embodiments of the present disclosure provide methods for forming features in a film stack that may be utilized to form stair-like structures with accurate profiles control in manufacturing three dimensional (3D) stacking of semiconductor chips. In one example, a method of etching a material layer disposed on a substrate using synchronized RF pulses includes providing an etching gas mixture into a processing chamber having a film stack disposed on a substrate, synchronously pulsing a RF source power and a RF bias power into the etching gas mixture at a ratio of less than 0.5, and etching the film stack disposed on the substrate.

Abstract translation: 本公开的实施例提供了用于形成膜堆叠中的特征的方法，其可以用于在制造半导体芯片的三维（3D）堆叠中形成具有精确轮廓控制的阶梯状结构。 在一个示例中，使用同步RF脉冲蚀刻设置在基板上的材料层的方法包括：将蚀刻气体混合物提供到具有设置在基板上的膜堆叠的处理室中，将RF源功率和RF偏置功率同步地脉冲 蚀刻气体混合物的比例小于0.5，并蚀刻设置在基底上的薄膜叠层。

公开(公告)号：US20150064914A1

公开(公告)日：2015-03-05

申请号：US14474841

申请日：2014-09-02

Applicant: Applied Materials, Inc.

Inventor： Byungkook KONG ,  Jun Wan KIM ,  Wonmo AHN ,  Jeong Hyun YOO ,  Hun Sang KIM

IPC: H01L21/033

CPC classification number: H01L21/0332 ,  H01J37/32082 ,  H01J37/3244 ,  H01J2237/334 ,  H01L21/31122 ,  H01L21/6831

Abstract: In one embodiment, a method is proposed for etching a boron dope hardmask layer. The method includes flowing a process gas comprising at least CH4 into a processing chamber. Forming a plasma in the process chamber from the process gas and etching the boron doped hardmask layer in the presence of the plasma. In other embodiments, the process gas utilized to etch the boron doped hardmask layer includes CH4, Cl2, SF6 and O2.

Abstract translation: 在一个实施例中，提出了一种用于蚀刻硼掺杂硬掩模层的方法。 该方法包括使包含至少CH 4的处理气体流入处理室。 在处理气体中形成等离子体，并在等离子体存在下蚀刻硼掺杂的硬掩模层。 在其他实施方案中，用于蚀刻硼掺杂的硬掩模层的工艺气体包括CH 4，Cl 2，SF 6和O 2。