公开(公告)号：US20250113522A1

公开(公告)日：2025-04-03

申请号：US18899327

申请日：2024-09-27

Applicant: Applied Materials, Inc.

Inventor： Ruiying HAO ,  Fredrick David FISHBURN ,  Raghuveer Satya MAKALA ,  Thomas John KIRSCHENHEITER ,  Balasubramanian PRANATHARTHIHARAN

IPC: H01L29/775 ,  H01L21/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: Three-dimensional (3D) memory structures and methods of formation of same are provided herein. In some embodiments, a 3D memory fabrication structure includes: a base silicon (Si) layer; a silicon germanium (SiGe) layer disposed above the base Si layer; and a doped silicon (Si) layer disposed on at least one side of the SiGe layer, wherein the doped Si layer contains a dopant that is at least one of carbon (C) or boron (B).

公开(公告)号：US20250132163A1

公开(公告)日：2025-04-24

申请号：US18894659

申请日：2024-09-24

Applicant: Applied Materials, Inc.

Inventor： Raghuveer Satya MAKALA ,  Ruiying HAO ,  Devika S. GRANT ,  Balasubramanian PRANATHARTHIHARAN

IPC: H01L21/308 ,  H01L21/02 ,  H01L21/033 ,  H01L23/00

Abstract: Embodiments of the present disclosure include a thinned device structure and method of forming a thinned device structure. Embodiments of the disclosure provided herein include the use of engineered epitaxial (Epi) layers that are formed on a base substrate. The engineered epitaxial layers include two or more epitaxial layers that each include materials that allow at least one of the two or more epitaxial layers to be selectively removed from the other layer(s). In some embodiments, one of the two or more formed epitaxial layers has etch selectivity (e.g., wet and/or dry etch selectivity) to materials disposed on either side of the formed layer.

公开(公告)号：US20250075321A1

公开(公告)日：2025-03-06

申请号：US18652608

申请日：2024-05-01

Applicant: Applied Materials, Inc.

Inventor： Fredrick FISHBURN ,  Hao ZHANG ,  Zhijun CHEN ,  Johanes SWENBERG ,  Christopher S. OLSEN ,  Hansel LO ,  Kristopher Mikael KOSKELA ,  Hoi-Sung CHUNG ,  Chang Seok KANG ,  Raghuveer Satya MAKALA

IPC: C23C16/455 ,  C23C16/04 ,  C23C16/34 ,  C23C16/56

Abstract: A method for forming an oxide layer includes forming a protective interlayer oxide on sidewalls of a trench formed on a substrate, forming a silicon nitride layer on the protective interlayer oxide, by a plasma-enhanced atomic layer deposition (PE ALD) process utilizing nitrogen-containing process gas, the silicon nitride layer having a concentration gradient of nitrogen varying from high concentration away from the protective interlayer oxide to low concentration near the protective interlayer oxide, and performing a conversion process to oxidize the formed silicon nitride layer to at least partially convert the formed silicon nitride layer to a silicon oxide layer.