Semiconductor device processing tools and methods for patterning substrates
    1.
    发明授权
    Semiconductor device processing tools and methods for patterning substrates 有权
    用于图案化衬底的半导体器件加工工具和方法

    公开(公告)号:US09431267B2

    公开(公告)日:2016-08-30

    申请号:US14093503

    申请日:2013-12-01

    CPC classification number: H01L21/3088 H01L21/3086 H01L21/67184 H01L21/67207

    Abstract: In some embodiments, an electronic device processing system is provided that includes a processing tool having a first subsystem configured to carry out a first subset of processes on a substrate having pattern features, the first subsystem including a first conformal deposition chamber and a first etch chamber. The processing tool includes a second subsystem coupled to the first subsystem and configured to carry out a second subset of processes on the substrate, the second subsystem including a second conformal deposition chamber and a second etch chamber. The processing tool is configured to employ the first and second subsystems to perform pitch division on the substrate within the processing tool so as to form a reduced-pitch pattern on the substrate. Numerous other embodiments are provided.

    Abstract translation: 在一些实施例中,提供一种电子设备处理系统,其包括具有第一子系统的处理工具,第一子系统被配置为在具有图案特征的基板上执行第一子进程,第一子系统包括第一共形沉积室和第一蚀刻室 。 所述处理工具包括耦合到所述第一子系统并被配置为在所述衬底上执行第二子进程的第二子系统,所述第二子系统包括第二共形沉积室和第二蚀刻室。 处理工具被配置为使用第一和第二子系统在处理工具内的基板上执行螺距分割,以便在基板上形成减小的间距图案。 提供了许多其他实施例。

    SEMICONDUCTOR DEVICE PROCESSING TOOLS AND METHODS FOR PATTERNING SUBSTRATES
    2.
    发明申请
    SEMICONDUCTOR DEVICE PROCESSING TOOLS AND METHODS FOR PATTERNING SUBSTRATES 有权
    半导体器件加工工具和方法用于绘制衬底

    公开(公告)号:US20140154887A1

    公开(公告)日:2014-06-05

    申请号:US14093503

    申请日:2013-12-01

    CPC classification number: H01L21/3088 H01L21/3086 H01L21/67184 H01L21/67207

    Abstract: In some embodiments, an electronic device processing system is provided that includes a processing tool having a first subsystem configured to carry out a first subset of processes on a substrate having pattern features, the first subsystem including a first conformal deposition chamber and a first etch chamber. The processing tool includes a second subsystem coupled to the first subsystem and configured to carry out a second subset of processes on the substrate, the second subsystem including a second conformal deposition chamber and a second etch chamber. The processing tool is configured to employ the first and second subsystems to perform pitch division on the substrate within the processing tool so as to form a reduced-pitch pattern on the substrate. Numerous other embodiments are provided.

    Abstract translation: 在一些实施例中,提供一种电子设备处理系统,其包括具有第一子系统的处理工具,第一子系统被配置为在具有图案特征的基板上执行第一子进程,第一子系统包括第一共形沉积室和第一蚀刻室 。 所述处理工具包括耦合到所述第一子系统并被配置为在所述衬底上执行第二子进程的第二子系统,所述第二子系统包括第二共形沉积室和第二蚀刻室。 处理工具被配置为使用第一和第二子系统在处理工具内的基板上执行螺距分割,以便在基板上形成减小的间距图案。 提供了许多其他实施例。

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