公开(公告)号：US11764058B2

公开(公告)日：2023-09-19

申请号：US17487596

申请日：2021-09-28

Applicant: Applied Materials, Inc.

Inventor： Arvind Kumar ,  Mahendra Pakala ,  Ellie Y. Yieh ,  John Tolle ,  Thomas Kirschenheiter ,  Anchuan Wang ,  Zihui Li

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L21/306 ,  H10B12/00

CPC classification number: H01L21/02532 ,  H01L21/0259 ,  H01L21/0262 ,  H01L21/02579 ,  H01L21/30604 ,  H01L29/0665 ,  H01L29/66742 ,  H01L29/78696 ,  H10B12/05 ,  H10B12/30

Abstract: Methods of reducing wafer bowing in 3D DRAM devices are described using a 3-color process. A plurality of film stacks are formed on a substrate surface, each of the film stacks comprises two doped SiGe layers having different dopant amounts and/or Si:Ge ratios and a doped silicon layer. 3D DRAM devices are also described.

公开(公告)号：US20230326925A1

公开(公告)日：2023-10-12

申请号：US17715331

申请日：2022-04-07

Applicant: Applied Materials, Inc.

Inventor： Andrew Anthony Cockburn ,  Vanessa Pena ,  Daniel Philippe Cellier ,  John Tolle ,  Thomas Kirschenheiter ,  Wei Hong ,  Ellie Y. Yieh ,  Mehul Naik ,  Seshadri Ramaswami

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/30604 ,  H01L21/823807 ,  H01L29/66742

Abstract: Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers having a reduced selective removal rate. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise doped silicon germanium (SiGe).

公开(公告)号：US12262559B2

公开(公告)日：2025-03-25

申请号：US17715331

申请日：2022-04-07

Applicant: Applied Materials, Inc.

Inventor： Andrew Anthony Cockburn ,  Vanessa Pena ,  Daniel Philippe Cellier ,  John Tolle ,  Thomas Kirschenheiter ,  Wei Hong ,  Ellie Y. Yieh ,  Mehul Naik ,  Seshadri Ramaswami

IPC: H10D30/67 ,  H01L21/02 ,  H01L21/306 ,  H10D30/01 ,  H10D62/10 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85

Abstract: Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers having a reduced selective removal rate. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise doped silicon germanium (SiGe).

公开(公告)号：US20230102558A1

公开(公告)日：2023-03-30

申请号：US17487596

申请日：2021-09-28

Applicant: Applied Materials, Inc.

Inventor： Arvind Kumar ,  Mahendra Pakala ,  Ellie Y. Yieh ,  John Tolle ,  Thomas Kirschenheiter ,  Anchuan Wang ,  Zihui Li

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: Methods of reducing wafer bowing in 3D DRAM devices are described using a 3-color process. A plurality of film stacks are formed on a substrate surface, each of the film stacks comprises two doped SiGe layers having different dopant amounts and/or Si:Ge ratios and a doped silicon layer. 3D DRAM devices are also described.