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41 条记录 (耗时 0.025 秒)

    Integrated contact silicide with tunable work functions
    1.
    发明授权
    Integrated contact silicide with tunable work functions 有权

    公开(公告)号：US11626288B2

    公开(公告)日：2023-04-11

    申请号：US17389772

    申请日：2021-07-30

    申请人： Applied Materials, Inc.

    发明人： Raymond Hung ,  Mehul Naik ,  Michael Haverty

    IPC分类号： H01L21/285 ,  H01L29/45 ,  H01L29/47 ,  H01L29/40 ,  H01L29/417

    摘要： Methods for reducing interface resistance of semiconductor devices leverage dual work function metal silicide. In some embodiments, a method may comprise selectively depositing a metal silicide layer on an Epi surface and adjusting a metal-to-silicon ratio of the metal silicide layer during deposition to alter a work function of the metal silicide layer based on whether the Epi surface is a P type Epi surface or an N type Epi surface to achieve a Schottky barrier height of less than 0.5 eV. The work function for a P type Epi surface may be adjusted to a value of approximately 5.0 eV and the work function for an N type Epi surface may be adjusted to a value of approximately 3.8 eV. The deposition of the metal silicide layer on the Epi surface may be performed prior to deposition of a contact etch stop layer and an activation anneal.

    Fully aligned subtractive processes and electronic devices therefrom
    2.
    发明授权
    Fully aligned subtractive processes and electronic devices therefrom 有权

    公开(公告)号：US11410885B2

    公开(公告)日：2022-08-09

    申请号：US16864623

    申请日：2020-05-01

    申请人： Applied Materials, Inc.

    发明人： He Ren ,  Hao Jiang ,  Mehul Naik

    IPC分类号： H01L21/768 ,  H01L21/3213 ,  H01L23/522

    摘要： Methods of forming fully aligned vias connecting two metal lines extending in two directions are described. The fully aligned via is aligned with the first metal line and the second metal line along both directions. A third metal layer is patterned on a top of a second metal layer in electrical contact with a first metal layer. The patterned third metal layer is misaligned from the top of the second metal layer. The second metal layer is recessed to expose sides of the second metal layer and remove portions not aligned sides of the third metal layer.

    Process integration approach for selective metal via fill
    5.
    发明授权
    Process integration approach for selective metal via fill 有权

    公开(公告)号：US11164780B2

    公开(公告)日：2021-11-02

    申请号：US16435121

    申请日：2019-06-07

    申请人： APPLIED MATERIALS, INC.

    发明人： Shi You ,  He Ren ,  Mehul Naik ,  Yi Xu ,  Feng Chen

    IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L21/02

    摘要： Methods and apparatus for an interconnect formed on a substrate and a method of forming the interconnect thereon. In embodiments, the methods include etching through a hard mask disposed atop a low-k dielectric layer to form a via through the low-k dielectric layer and expose a conductive surface; contacting the conductive surface with dilute hydrofluoric acid to remove contaminants therefrom; removing the hard mask disposed atop the low-k dielectric layer; and applying a remote hydrogen plasma to the conductive surface to form an exposed portion of the conductive surface.

    Damage free metal conductor formation
    7.
    发明授权
    Damage free metal conductor formation 有权

    公开(公告)号：US10685849B1

    公开(公告)日：2020-06-16

    申请号：US16400737

    申请日：2019-05-01

    申请人： Applied Materials, Inc.

    发明人： He Ren ,  Jong Mun Kim ,  Maximillian Clemons ,  Minrui Yu ,  Mehul Naik ,  Chentsau Ying

    IPC分类号： H01L21/321 ,  H01L21/3213

    摘要： Exemplary methods of etching semiconductor substrates may include flowing a halogen-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having a conductive material and an overlying mask material. The conductive material may be characterized by a first surface in contact with the mask material, and the mask material may define an edge region of the conductive material. The methods may include contacting the edge region of the conductive material with the halogen-containing precursor and the oxygen-containing precursor. The methods may include etching in a first etching operation the edge region of the conductive material to a partial depth through the conductive material to produce a footing of conductive material protruding along the edge region of the conductive material. The methods may also include removing the footing of conductive material in a second etching operation.

    Method of dielectric material fill and treatment
    10.
    发明授权
    Method of dielectric material fill and treatment 有权

    公开(公告)号：US11615984B2

    公开(公告)日：2023-03-28

    申请号：US16848784

    申请日：2020-04-14

    申请人： APPLIED MATERIALS, INC.

    发明人： Shi You ,  He Ren ,  Naomi Yoshida ,  Nikolaos Bekiaris ,  Mehul Naik ,  Martin Jay Seamons ,  Jingmei Liang ,  Mei-Yee Shek

    IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/67

    摘要： Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material.