公开(公告)号：US20240321633A1

公开(公告)日：2024-09-26

申请号：US18123101

申请日：2023-03-17

Applicant: Applied Materials, Inc.

Inventor： Zhiyuan Wu ,  Zheng Ju ,  Feng Chen

IPC: H01L21/768

CPC classification number: H01L21/76861 ,  H01L21/76831 ,  H01L21/76876

Abstract: Methods for depositing ultra-thin films are disclosed. Some embodiments of the disclosure utilize ultra-thin films as barrier layers, liner layers, or nucleation layers to decrease interconnect resistance. Some embodiments advantageously provide continuous films with thicknesses of less than or equal to about 20 Å. Some embodiments advantageously provide films with decreased roughness.

公开(公告)号：US20210351136A1

公开(公告)日：2021-11-11

申请号：US16909148

申请日：2020-06-23

Applicant: Applied Materials, Inc.

Inventor： Gang Shen ,  Feng Chen ,  Yizhak Sabba ,  Tae Hong Ha ,  Xianmin Tang ,  Zhiyuan Wu ,  Wenjing Xu

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: Described are microelectronic device comprising a dielectric layer formed on a substrate, a feature 206 comprising a gap defined in the dielectric layer, a barrier layer on the dielectric layer, a two metal liner film on the barrier layer and a gap fill metal on the two metal liner. Embodiments provide a method of forming an microelectronic device comprising the two metal liner film on the barrier layer.

公开(公告)号：US12211743B2

公开(公告)日：2025-01-28

申请号：US17466732

申请日：2021-09-03

Applicant: Applied Materials, Inc.

Inventor： Ge Qu ,  Zhiyuan Wu ,  Feng Chen ,  Carmen Leal Cervantes ,  Yong Jin Kim ,  Kevin Kashefi ,  Xianmin Tang ,  Wenjing Xu ,  Lu Chen ,  Tae Hong Ha

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532

Abstract: Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A self-assembled monolayer (SAM) is formed on the bottom of the gap, and a barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.

公开(公告)号：US20240420997A1

公开(公告)日：2024-12-19

申请号：US18211502

申请日：2023-06-19

Applicant: Applied Materials, Inc.

Inventor： Yang Zhou ,  Jiajie Cen ,  Zhiyuan Wu ,  Ge Qu ,  Yong Jin Kim ,  Zheng Ju ,  Feng Chen ,  Kevin Kashefi

IPC: H01L21/768

Abstract: Methods of forming devices comprise forming a dielectric material on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include passivating a metal material at a bottom of the gap with an alkyl reactant to form a passivation layer on the metal material, the gap defined by the bottom and sidewalls comprising the dielectric material with having a barrier layer thereon. A metal liner is selectively deposited on the barrier layer on the sidewall over the passivation layer on the bottom.

公开(公告)号：US20240332075A1

公开(公告)日：2024-10-03

申请号：US18613918

申请日：2024-03-22

Applicant: Applied Materials, Inc.

Inventor： Jiajie Cen ,  Kevin Kashefi ,  Zhiyuan Wu ,  Yang Zhou ,  Yong Jin Kim ,  Carmen Leal Cervantes ,  Ge Qu ,  Zheng Ju

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76844 ,  H01L21/76846 ,  H01L23/5226 ,  H01L21/76882 ,  H01L23/53209 ,  H01L23/53238

Abstract: Methods of forming microelectronic devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include selectively depositing a first self-assembled monolayer (SAM) on the bottom of the gap; forming a barrier layer on the dielectric layer; selectively depositing a second self-assembled monolayer (SAM) on the barrier layer and on the bottom of the gap; treating the microelectronic device with a plasma to remove a first portion of the second self-assembled monolayer (SAM); selectively depositing a metal liner on the barrier layer on the sidewall; removing a second portion of the second self-assembled monolayer (SAM); and performing a gap fill process on the metal liner.

公开(公告)号：US20240258103A1

公开(公告)日：2024-08-01

申请号：US18422656

申请日：2024-01-25

Applicant: Applied Materials, Inc.

Inventor： Jiajie Cen ,  Ge Qu ,  Shinjae Hwang ,  Zheng Ju ,  Yang Zhou ,  Zhiyuan Wu ,  Feng Chen ,  Kevin Kashefi

IPC: H01L21/02 ,  H01L21/768

CPC classification number: H01L21/02274 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76843

Abstract: Embodiments of the disclosure relate to methods for forming electrical interconnects. Additional embodiments provide methods of forming and treating barrier and liner layers to improve film and material properties. In some embodiments, the resulting composite layers provide improved resistivity, decrease void formation and improve device reliability.

公开(公告)号：US11784127B2

公开(公告)日：2023-10-10

申请号：US17858274

申请日：2022-07-06

Applicant: Applied Materials, Inc.

Inventor： Wenjing Xu ,  Feng Chen ,  Tae Hong Ha ,  Xianmin Tang ,  Lu Chen ,  Zhiyuan Wu

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76849 ,  H01L23/5226

Abstract: Electronic devices and methods of forming electronic devices using a ruthenium or doped ruthenium liner and cap layer are described. A liner with a ruthenium layer and a cobalt layer is formed on a barrier layer. A conductive fill forms a second conductive line in contact with the first conductive line.

公开(公告)号：US10438849B2

公开(公告)日：2019-10-08

申请号：US15137245

申请日：2016-04-25

Applicant: APPLIED MATERIALS, INC.

Inventor： He Ren ,  Jie Zhou ,  Guannan Chen ,  Michael W. Stowell ,  Bencherki Mebarki ,  Mehul Naik ,  Srinivas D. Nemani ,  Nikolaos Bekiaris ,  Zhiyuan Wu

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532

Abstract: An integrated circuit is fabricated by chemical vapor deposition or atomic layer deposition of a metal film to metal film.

公开(公告)号：US20240420996A1

公开(公告)日：2024-12-19

申请号：US18209035

申请日：2023-06-13

Applicant: Applied Materials, Inc.

Inventor： Jiajie Cen ,  Zhiyuan Wu ,  Kevin Kashefi ,  Yong Jin Kim ,  Yang Zhou ,  Zheng Ju

IPC: H01L21/768 ,  H01J37/32 ,  H01L21/311

Abstract: Methods of forming microelectronic devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include forming a hardmask on the dielectric layer; selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap and on the hardmask; treating the microelectronic device with a plasma to remove the self-assembled monolayer (SAM) from the hardmask; forming a barrier layer on the dielectric layer and on the hardmask; selectively depositing a metal liner on the barrier layer on the sidewall; and performing a gap fill process on the metal liner.

公开(公告)号：US11764157B2

公开(公告)日：2023-09-19

申请号：US17383361

申请日：2021-07-22

Applicant: Applied Materials, Inc.

Inventor： Wenjing Xu ,  Feng Chen ,  Tae Hong Ha ,  Xianmin Tang ,  Lu Chen ,  Zhiyuan Wu

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76849 ,  H01L23/5226

Abstract: Electronic devices and methods of forming electronic devices using a ruthenium or doped ruthenium liner and cap layer are described. A liner with a ruthenium layer and a cobalt layer is formed on a barrier layer. A conductive fill forms a second conductive line in contact with the first conductive line.