公开(公告)号：US20150363352A1

公开(公告)日：2015-12-17

申请号：US14482780

申请日：2014-09-10

Applicant: Applied Micro Circuits Corporation

Inventor： Arun JANGITY

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F13/16 ,  G11C5/063 ,  G11C7/1039 ,  G11C7/1048 ,  G11C7/222

Abstract: A memory bus comprising a plurality of latches arranged sequentially between a source node and a destination node of a channel of the memory bus; and a pulse generator. The pulse generator is operable to generate a sequence of pulses, each sequential pulse to be simultaneously received by the plurality of latches. A pulse is generated for each edge of a clock signal. A first latch of the plurality of latches is operable to pass on a first data sample while a first pulse is received by the first latch of the plurality of latches. A second latch of the plurality of latches is operable to pass on a second data sample towards the first latch of the plurality of latches while the first pulse is simultaneously received by the first and second latches of the plurality of latches.

Abstract translation: 存储器总线，包括顺序地布置在存储器总线的通道的源节点和目的地节点之间的多个锁存器; 和脉冲发生器。 脉冲发生器可操作以产生脉冲序列，每个顺序脉冲将由多个锁存器同时接收。 为时钟信号的每个边沿产生一个脉冲。 当多个锁存器的第一锁存器接收到第一脉冲时，多个锁存器的第一锁存器可操作以传递第一数据采样。 多个锁存器的第二锁存器可操作以使第二数据采样朝着多个锁存器的第一锁存器传递，同时第一脉冲由多个锁存器的第一和第二锁存器同时接收。