公开(公告)号：US06486821B1

公开(公告)日：2002-11-26

申请号：US09911331

申请日：2001-07-23

申请人： Arlo J. Aude ,  Laurence D. Lewicki ,  Jitendra Mohan

发明人： Arlo J. Aude ,  Laurence D. Lewicki ,  Jitendra Mohan

IPC分类号： H03M112

CPC分类号： H03F1/086

摘要： There is disclosed an amplifier for operating from a power supply having a first voltage level. The amplifier comprises: 1) a plurality of thick-oxide field effect transistors, each of the plurality of thick-oxide field effect transistors having a relatively thick oxide layer and fabricated using a first process such that the each thick-oxide field effect transistor can withstand a gate-to-source difference, a gate-to-drain difference, and a gate-to-bulk difference at least equal to a first maximum operating voltage, wherein the first. maximum operating voltage is at least equal to the first voltage level; and 2) a first thin-oxide field effect transistor coupled to a first input of the amplifier, the first thin-oxide field effect transistor having a relatively thin oxide layer and fabricated using a second process such that the first thin-oxide field effect transistor can withstand a gate-to-source difference, a gate-to-drain difference, and a gate-to-bulk difference at least equal to a second maximum operating voltage, wherein the second maximum operating voltage is less than the first voltage level.

摘要翻译： 公开了一种用于从具有第一电压电平的电源操作的放大器。 放大器包括：1）多个厚氧化物场效应晶体管，多个厚氧化物场效应晶体管中的每一个具有相对较厚的氧化物层，并且使用第一工艺制造，使得每个厚氧化物场效应晶体管可以 承受栅极至源极的差异，栅极至漏极差异以及至少等于第一最大工作电压的栅极与体积之差，其中第一。 最大工作电压至少等于第一电压电平; 以及2）耦合到所述放大器的第一输入的第一薄氧化物场效应晶体管，所述第一薄氧化物场效应晶体管具有相对薄的氧化物层，并且使用第二工艺制造，使得所述第一薄氧化物场效应晶体管 可以承受栅极至源极的差异，栅极至漏极差异以及至少等于第二最大工作电压的栅极至体积差异，其中第二最大工作电压小于第一电压电平。

公开(公告)号：US06559787B1

公开(公告)日：2003-05-06

申请号：US09911233

申请日：2001-07-23

申请人： Arlo J. Aude ,  Laurence D. Lewicki ,  Jitendra Mohan

发明人： Arlo J. Aude ,  Laurence D. Lewicki ,  Jitendra Mohan

IPC分类号： H03M138

CPC分类号： H03K3/013 ,  H03K3/356139 ,  H03K5/2481 ,  H03K5/249

摘要： There is disclosed a comparator comprising: 1) a first comparison circuit capable of receiving an input signal, wherein the first comparison circuit is enabled and compares the signal when a received LATCH signal is enabled and is disabled when the received LATCH signal is disabled; and 2) a second comparison circuit coupled to the input signal in parallel with the first comparison circuit, wherein an input stage of the second comparison circuit is substantially identical to an input stage of the first comparison circuit. The second comparison circuit is enabled and compares the input signal when the received LATCH is signal is disabled and is disabled when the received LATCH signal is enabled.

摘要翻译： 公开了一种比较器，包括：1）能够接收输入信号的第一比较电路，其中所述第一比较电路被使能，并且当所接收的LATCH信号被使能时将所述信号进行比较，并且当所接收的LATCH信号被禁止时被禁用; 以及2）与所述第一比较电路并联耦合到所述输入信号的第二比较电路，其中所述第二比较电路的输入级基本上与所述第一比较电路的输入级相同。 当接收的LATCH信号被禁止时，第二比较电路被使能并比较输入信号，并且当所接收的LATCH信号被使能时被禁止。

公开(公告)号：US06859387B1

公开(公告)日：2005-02-22

申请号：US09569954

申请日：2000-05-12

申请人： Arlo J. Aude ,  Laurence D. Lewicki

发明人： Arlo J. Aude ,  Laurence D. Lewicki

IPC分类号： G06F7/48 ,  H03M1/06 ,  H03M1/12 ,  H03M1/38 ,  H03M1/44

CPC分类号： G06F7/4824 ,  H03M1/0695 ,  H03M1/44

摘要： Three-state binary adders are disclosed for use in pipelined analog-to-digital converters. According to one advantageous embodiment, a three-state binary adder is provided for use in a digital signal processing system. The three-state binary adder is operable to generate binary codes consisting of three states, namely, “00”, “01” and “10.”

摘要翻译： 公开了用于流水线模数转换器的三态二进制加法器。 根据一个有利的实施例，提供一种用于数字信号处理系统中的三态二进制加法器。 三态二进制加法器可操作以产生由三个状态组成的二进制码，即“00”，“01”和“10”。

公开(公告)号：US08416112B2

公开(公告)日：2013-04-09

申请号：US13187674

申请日：2011-07-21

申请人： Arlo J. Aude ,  Steven E. Finn

发明人： Arlo J. Aude ,  Steven E. Finn

IPC分类号： H03M1/80

CPC分类号： H03M1/747

摘要： Circuitry and method for digital-to-analog current signal conversion with phase interpolation. For an n-bit digital-to-analog converter (DAC), the number 2n control bits normally required can be reduced to 2(n-1) by jointly controlling pairs of the current sources with one of the 2(n-1) current control bits and inverses of two other ones of the 2(n-1) current control bits.

摘要翻译： 具有相位插值的数模转换电流信号转换的电路和方法。 对于n位数模转换器（DAC），通过使用2（n-1）中的一个共同控制电流源对，通常需要的2n个控制位可以减少到2（n-1） 2（n-1）个电流控制位中的另外两个的当前控制位和反相。

公开(公告)号：US20130021082A1

公开(公告)日：2013-01-24

申请号：US13188194

申请日：2011-07-21

申请人： Arlo J. Aude ,  Soumye Chandramouli

发明人： Arlo J. Aude ,  Soumye Chandramouli

IPC分类号： H03L5/00

CPC分类号： H03F3/45179 ,  H03F3/45183 ,  H03F3/45668 ,  H03F2203/45394 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45434 ,  H03F2203/45544 ,  H03F2203/45594 ,  H03F2203/45702

摘要： Low voltage differential signaling (LVDS) circuitry and method for dynamically controlling the common mode voltage at the input of an LVDS receiver. The common mode voltage of the incoming LVDS signal is monitored. The common mode voltage at the input of the LVDS receiver is clamped at a clamp voltage when the common mode voltage of the incoming LVDS signal is less than a predetermined voltage, and allowed to track it otherwise.

摘要翻译： 低压差分信号（LVDS）电路和方法，用于动态控制LVDS接收机输入端的共模电压。 监视输入LVDS信号的共模电压。 当输入LVDS信号的共模电压小于预定电压时，LVDS接收器输入处的共模电压被钳位在钳位电压，否则允许跟踪。

公开(公告)号：US06710732B1

公开(公告)日：2004-03-23

申请号：US09569955

申请日：2000-05-12

申请人： Arlo J. Aude

发明人： Arlo J. Aude

IPC分类号： H03M112

CPC分类号： G06F7/4824 ,  H03M1/0695 ,  H03M1/44

摘要： Three-state binary adders with endpoint correction are employed in a digital signal processing system within a pipelined analog-to-digital converter. The adder is operable to add received signals. The endpoint correction circuitry, which is associated with the adder, is operable to (i) use ±½ full scale tip voltages and to (ii) generate over and under indicators.

摘要翻译： 在流水线模数转换器中的数字信号处理系统中采用具有端点校正的三态二进制加法器。 加法器可操作以添加接收的信号。 与加法器相关联的端点校正电路可操作为（i）使用±½满量程尖端电压，并且（ii）产生超过和低于指示器。

公开(公告)号：US08476934B2

公开(公告)日：2013-07-02

申请号：US13188243

申请日：2011-07-21

申请人： Arlo J. Aude ,  Soumya Chandramouli

发明人： Arlo J. Aude ,  Soumya Chandramouli

IPC分类号： H03K5/22

CPC分类号： H04L25/0274 ,  H04L25/06

摘要： Differential signal detection circuitry with an integrated reference voltage. The reference voltage is added as an offset to the output voltage, and its integration ensures that variations in the reference voltage closely track variations in the signal. Accordingly, the detection threshold for the signal being detected remains more consistent over variations in the circuit manufacturing process, power supply voltage and operating temperature.

摘要翻译： 具有集成参考电压的差分信号检测电路。 参考电压作为输出电压的偏移量相加，其积分可确保参考电压的变化密切跟踪信号的变化。 因此，正在检测的信号的检测阈值在电路制造过程，电源电压和工作温度的变化方面保持更一致。

公开(公告)号：US20130021186A1

公开(公告)日：2013-01-24

申请号：US13187674

申请日：2011-07-21

申请人： Arlo J. Aude ,  Steven E. Finn

发明人： Arlo J. Aude ,  Steven E. Finn

IPC分类号： H03M1/66 ,  G06F17/50

CPC分类号： H03M1/747

摘要： Circuitry and method for digital-to-analog current signal conversion with phase interpolation. For an n-bit digital-to-analog converter (DAC), the number 2n control bits normally required can be reduced to 2(n-1) by jointly controlling pairs of the current sources with one of the 2(n-1) current control bits and inverses of two other ones of the 2(n-1) current control bits.

摘要翻译： 具有相位插值的数模转换电流信号转换的电路和方法。 对于n位数模转换器（DAC），通过使用2（n-1）中的一个共同控制电流源对，通常需要的2n个控制位可以减少到2（n-1） 2（n-1）个电流控制位中的另外两个的当前控制位和反相。

公开(公告)号：US20130021081A1

公开(公告)日：2013-01-24

申请号：US13188243

申请日：2011-07-21

申请人： Arlo J. Aude ,  Soumya Chandramouli

发明人： Arlo J. Aude ,  Soumya Chandramouli

IPC分类号： H03L5/00 ,  G06F17/50

CPC分类号： H04L25/0274 ,  H04L25/06

摘要： Differential signal detection circuitry with an integrated reference voltage. The reference voltage is added as an offset to the output voltage, and its integration ensures that variations in the reference voltage closely track variations in the signal. Accordingly, the detection threshold for the signal being detected remains more consistent over variations in the circuit manufacturing process, power supply voltage and operating temperature.

摘要翻译： 具有集成参考电压的差分信号检测电路。 参考电压作为输出电压的偏移量相加，其积分可确保参考电压的变化密切跟踪信号的变化。 因此，正在检测的信号的检测阈值在电路制造过程，电源电压和工作温度的变化方面保持更一致。

公开(公告)号：US06445250B1

公开(公告)日：2002-09-03

申请号：US09569829

申请日：2000-05-12

申请人： Arlo J. Aude

发明人： Arlo J. Aude

IPC分类号： H03F345

CPC分类号： H03F3/45183

摘要： There is disclosed an amplifier comprising: 1) a plurality of cascaded NMOS differential amplifier stages, wherein a first one of the plurality of cascaded NMOS differential amplifier stages is coupled to at least one input signal; 2) a PMOS differential amplifier stage having a first input coupled to a first NMOS differential output of a last one of the plurality of cascaded NMOS differential amplifier stages and a second input coupled to a second NMOS differential output of the last cascaded NMOS differential amplifier stage, wherein the PMOS differential amplifier comprises a first diode-connected PMOS load transistor having a gate and a drain connected to ground and a second diode-connected PMOS load transistor having a gate and a drain connected to ground; and 3) an output differential amplifier stage comprising: a) load transistors comprising a third PMOS transistor having a gate and a drain connected together and a source connected to a power supply rail and a fourth PMOS transistor having a gate coupled to the third PMOS transistor gate and a source connected to the power supply rail; and b) a differential transistors pair comprising a first NMOS transistor having a gate coupled to a source of the first diode-connected PMOS load transistor and a drain coupled to a drain of the third PMOS transistor and a second NMOS transistor having a gate coupled to a source of the second diode-connected PMOS load transistor and a drain coupled to a drain of the fourth PMOS transistor.

摘要翻译： 公开了一种放大器，包括：1）多个级联的NMOS差分放大器级，其中多个级联的NMOS差分放大器级中的第一级与至少一个输入信号耦合; 2）PMOS差分放大器级，其具有耦合到多个级联NMOS差分放大器级中的最后一个的差分放大器级中的最后一个的第一NMOS差分输出的第一输入和耦合到最后级联NMOS差分放大器级的第二NMOS差分输出的第二输入 其中所述PMOS差分放大器包括具有连接到地的栅极和漏极的第一二极管连接的PMOS负载晶体管和具有连接到地的栅极和漏极的第二二极管连接的PMOS负载晶体管; 以及3）输出差分放大器级，包括：a）负载晶体管，其包括具有连接在一起的栅极和漏极的第三PMOS晶体管，以及连接到电源轨的源极和具有耦合到所述第三PMOS晶体管的栅极的第四PMOS晶体管 门和源极连接到电源轨; 以及b）差分晶体管对，其包括具有耦合到所述第一二极管连接的PMOS负载晶体管的源极的栅极的第一NMOS晶体管和耦合到所述第三PMOS晶体管的漏极的漏极和第二NMOS晶体管，所述第二NMOS晶体管具有耦合到 第二二极管连接的PMOS负载晶体管的源极和耦合到第四PMOS晶体管的漏极的漏极。