PERIPHERAL COMPONENT HANDLING OF MEMORY READ REQUESTS

    公开(公告)号:US20230267081A1

    公开(公告)日:2023-08-24

    申请号:US17678174

    申请日:2022-02-23

    Applicant: Arm Limited

    Abstract: Peripheral components, data processing systems and methods of operating such peripheral components and data processing systems are disclosed. The systems comprise an interconnect comprising a system cache, a peripheral component coupled to the interconnect, and a memory coupled to the interconnect. The peripheral component has a memory access request queue for queuing memory access requests in a receipt order. Memory access requests are issued to the interconnect in the receipt order. A memory read request is not issued to the interconnect until a completion response for all older memory write requests has been received from the interconnect. The peripheral component is responsive to receipt of a memory read request to issue a memory read prefetch request comprising a physical address to the interconnect and the interconnect is responsive to the memory read prefetch request to cause data associated with the physical address in the memory to be cached in the system cache.

    PCIE ROUTING
    2.
    发明申请

    公开(公告)号:US20230140069A1

    公开(公告)日:2023-05-04

    申请号:US17512758

    申请日:2021-10-28

    Applicant: Arm Limited

    Abstract: A data processing apparatus is provided that includes communication circuitry to transmit an interconnect message to a root port using a physical address mapped to the root port. Translation circuitry encapsulates, within the interconnect message to the root port, a Peripheral Component Interconnect Express (PCIe) message to a destination, the PCIe message having routing information encoded as a PCIe bus number associated with the destination.

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