公开(公告)号：US20190196990A1

公开(公告)日：2019-06-27

申请号：US15850296

申请日：2017-12-21

Applicant: Arm Limited

Inventor： Arthur Brian LAUGHTON ,  Sean James SALISBURY ,  Chiranjeev ACHARYA ,  Eduard VARDANYAN

IPC: G06F13/16 ,  G06F13/42

CPC classification number: G06F13/1678 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/4018 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2213/0026 ,  G06F2213/4004

Abstract: An interconnect for providing data access between nodes of an integrated circuit, comprises a predetermined type of ingress port comprising routing circuitry responsive to a read-triggering request received from a requesting node to select from a selected egress port via which signals are to be routed to a destination node to control the destination node to return at least one read response dependent on data read from a target storage location. In response to the read-triggering request, the routing circuitry obtains a relative data width indication specifying whether read responses received at the selected egress port have a narrower data width than read responses to be provided to the requesting node by the predetermined type of ingress port, and controls allocation of resource for handling the read-triggering request or the at least one read response depending on the relative data width indication.

公开(公告)号：US20230267081A1

公开(公告)日：2023-08-24

申请号：US17678174

申请日：2022-02-23

Applicant: Arm Limited

Inventor： Jacob JOSEPH ,  Tessil THOMAS ,  Arthur Brian LAUGHTON ,  Anitha KONA ,  Jamshed JALAL

IPC: G06F13/16 ,  G06F12/0862 ,  G06F12/1045 ,  G06F12/0891

CPC classification number: G06F13/1668 ,  G06F13/161 ,  G06F12/0862 ,  G06F12/1054 ,  G06F12/1063 ,  G06F12/0891

Abstract: Peripheral components, data processing systems and methods of operating such peripheral components and data processing systems are disclosed. The systems comprise an interconnect comprising a system cache, a peripheral component coupled to the interconnect, and a memory coupled to the interconnect. The peripheral component has a memory access request queue for queuing memory access requests in a receipt order. Memory access requests are issued to the interconnect in the receipt order. A memory read request is not issued to the interconnect until a completion response for all older memory write requests has been received from the interconnect. The peripheral component is responsive to receipt of a memory read request to issue a memory read prefetch request comprising a physical address to the interconnect and the interconnect is responsive to the memory read prefetch request to cause data associated with the physical address in the memory to be cached in the system cache.

公开(公告)号：US20230140069A1

公开(公告)日：2023-05-04

申请号：US17512758

申请日：2021-10-28

Applicant: Arm Limited

Inventor： Tessil THOMAS ,  Anitha KONA ,  Jacob JOSEPH ,  Arthur Brian LAUGHTON ,  Nandakishore SASTRY

IPC: G06F13/42

Abstract: A data processing apparatus is provided that includes communication circuitry to transmit an interconnect message to a root port using a physical address mapped to the root port. Translation circuitry encapsulates, within the interconnect message to the root port, a Peripheral Component Interconnect Express (PCIe) message to a destination, the PCIe message having routing information encoded as a PCIe bus number associated with the destination.

公开(公告)号：US20200250281A1

公开(公告)日：2020-08-06

申请号：US16267498

申请日：2019-02-05

Applicant: Arm Limited

Inventor： Sean James SALISBURY ,  Zheng XU ,  Arthur Brian LAUGHTON ,  Charles Filip BREJ

IPC: G06F17/50 ,  G06F9/30

Abstract: A method comprises generating, using a computer, an integrated circuit layout including a plurality of data handling nodes interconnected by routing circuitry defining data packet routes between the plurality of data handling nodes; for a transaction source node configured to generate data packets associated with a data handling translation between that transaction source node and a transaction target node and having one or more routing data fields controlling routing of the data packet, detecting, using the computer, a difference between a first routing controlled by the one or more routing data fields and a selected second routing provided by the integrated circuit layout; and providing, using the computer, one or more data mapping nodes in the integrated circuit layout to map an initial value of one or more of the routing data fields of a data packet generated by the transaction source node to a mapped data value, so that the mapped data value controls routing of the data packet using the selected second routing.

公开(公告)号：US20160103776A1

公开(公告)日：2016-04-14

申请号：US14874801

申请日：2015-10-05

Applicant: ARM LIMITED

Inventor： Andrew David TUNE ,  Arthur Brian LAUGHTON ,  Daniel Adam SARA ,  Sean James SALISBURY ,  Peter Andrew RIOCREUX

IPC: G06F13/364 ,  G06F15/78 ,  G06F13/42

CPC classification number: G06F13/364 ,  G06F13/4282

Abstract: Interconnect circuitry 10 for connecting transaction masters 4, 6, 8 to transaction slaves 12, 14 includes response modification circuitry 18. The response modification circuitry includes shortlist buffer circuitry 28 storing identification for modification target transaction responses. The response modification circuitry 18 uses this identification data to identify among a stream of transaction responses in transit a modification target transaction response. The response modification circuitry 18 then serves to form a modified transaction response to be sent in place of the modification target transaction response to the transaction master 4, 6, 8.

Abstract translation: 用于将交易主机4,6,8连接到交易从站12,14的互连电路10包括响应修改电路18.响应修改电路包括存储用于修改目标事务响应的标识的候选列表缓冲器电路28。 响应修改电路18使用该识别数据来识别传送中的事务响应流中的修改目标事务响应。 响应修改电路18然后用于形成被修改的事务响应，以代替对交易主机4,6,8的修改目标事务响应。

公开(公告)号：US20190179783A1

公开(公告)日：2019-06-13

申请号：US16200205

申请日：2018-11-26

Applicant: Arm Limited

Inventor： Arthur Brian LAUGHTON ,  Chiranjeev ACHARYA ,  Eduard VARDANYAN

IPC: G06F13/20 ,  G06F13/40 ,  G06F17/50

Abstract: Routing circuitry 400 is provided for routing transaction requests to a selected destination node. The routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Request regulators 401, 402, 403 are provided to monitor resource usage for read, atomic and write requests, and issue circuitry 431 controls the issuing of a transaction request received from a requesting node, in dependence on resource usage monitoring performed by the request regulators. The issue circuitry controls the issuing of atomic requests in dependence on the resource usage monitored by the write request regulator and the resource usage monitored by the atomic request regulator.

公开(公告)号：US20190163400A1

公开(公告)日：2019-05-30

申请号：US16148295

申请日：2018-10-01

Applicant: Arm Limited

Inventor： Chiranjeev ACHARYA ,  Sean James SALISBURY ,  Eduard VARDANYAN ,  Arthur Brian LAUGHTON

IPC: G06F3/06 ,  G06F17/50

Abstract: Data access routing circuitry 4, 6 is provided for routing data access request to a selected destination node. The data access routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Resource allocation circuitry 70, 71 is provided to control allocation of resource for handling data access requests which require a read response. The resource allocation circuitry 70, 71 reserves resource for handling the at least one type of atomic data access request and prevents use of the reserved resource 76 for handling read requests.

公开(公告)号：US20180285145A1

公开(公告)日：2018-10-04

申请号：US15478443

申请日：2017-04-04

Applicant: ARM Limited

Inventor： Chiranjeev ACHARYA ,  Arthur Brian LAUGHTON ,  Sean James SALISBURY

IPC: G06F9/46 ,  G06F13/364 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F9/467 ,  G06F5/14 ,  G06F13/1673 ,  G06F13/364 ,  G06F13/4282 ,  G06F2205/126 ,  Y02D10/14 ,  Y02D10/151

Abstract: Transaction handling apparatus comprises a response buffer; and tracking circuitry to store data defining each transaction issued by one or more transaction master devices and to control routing of a transaction response to a given transaction either to the response buffer or as an output to the transaction master device which issued the given transaction; the response buffer being configured to access an indicator for each buffered transaction response indicating whether a response has been output by the apparatus for a previously issued transaction, on which that buffered transaction response depends, and to output the buffered transaction response to the transaction master device which issued that transaction when the previously issued transaction has already been output by the apparatus.

公开(公告)号：US20180232168A1

公开(公告)日：2018-08-16

申请号：US15430824

申请日：2017-02-13

Applicant: ARM Limited

Inventor： Arthur Brian LAUGHTON

IPC: G06F3/06

Abstract: An apparatus for processing data 2 contains multiple power domains which may be in a non-retaining power state or a retaining power state. If a power domain is in a non-retaining power state in which it is not able to retain a copy of a stored parameter value and it is switched into a retaining power state in which it requires a copy of that parameter value, then it fetches the parameter value from a store within another power domain. One of the power domains contains a master copy of the parameter value to which writes changing in the parameter value are made. At least one of the other power domains fetches a copy of the parameter value if required from a power domain other than the power domain containing the master copy.