公开(公告)号：US11561795B2

公开(公告)日：2023-01-24

申请号：US16834833

申请日：2020-03-30

Applicant: Arm Limited

Inventor： Jens Olson ,  John Wakefield Brothers, III ,  Jared Corey Smolens ,  Chi-wen Cheng ,  Daren Croxford ,  Sharjeel Saeed ,  Dominic Hugo Symes

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/345 ,  G06F7/499 ,  G06F7/57

Abstract: Herein described is a method of operating an accumulation process in a data processing apparatus. The accumulation process comprises a plurality of accumulations which output a respective plurality of accumulated values, each based on a stored value and a computed value generated by a data processing operation. The method comprises storing a first accumulated value, the first accumulated value being one of said plurality of accumulated values, into a first storage device comprising a plurality of single-bit storage elements; determining that a predetermined trigger has been satisfied with respect to the accumulation process; and in response to the determining, storing at least a portion of a second accumulated value, the second accumulated value being one of said plurality of accumulated values, into a second storage device.

公开(公告)号：US12072808B2

公开(公告)日：2024-08-27

申请号：US18063478

申请日：2022-12-08

Applicant: Arm Limited

Inventor： Jens Olson ,  Jared Corey Smolens

IPC: G06F12/0875

CPC classification number: G06F12/0875 ,  G06F2212/1024 ,  G06F2212/221 ,  G06F2212/452

Abstract: A processor comprising a first storage managed as a circular buffer to store a plurality of data structures. Each data structure comprises: an identifier, a size indicator and first data associated with instructions for execution of a task. The processor is configured for searching for a data structure in the first storage. A data structure subsequent to the tail data structure can be located using a storage address in the first storage of a tail data structure and the size indicator of all data structures preceding the second data structure among the plurality of data structures. When a data structure is found, the task may be executed based at least in part on the first data of the found data structure.

公开(公告)号：US12288091B2

公开(公告)日：2025-04-29

申请号：US17474568

申请日：2021-09-14

Applicant: Arm Limited

Inventor： Eric Kunze ,  Jared Corey Smolens ,  Aaron DeBattista ,  Elliot Maurice Simon Rosemarine

IPC: G06F9/46 ,  G06F9/38 ,  G06F9/448 ,  G06F9/48

Abstract: Aspects of the present disclosure relate to apparatus comprising execution circuitry comprising at least one execution unit to execute program instructions, and control circuitry. The control circuitry receives a stream of processing instructions, and issues each received instruction to one of said at least one execution unit. Responsive to determining that a first type of context switch is to be performed from an initial context to a new context, issuing continues until a pre-emption point in the stream of processing instructions is reached. Responsive to reaching the pre-emption point, state information is stored, and the new context is switched to. Responsive to determining that a context switch is to be performed to return from the new context to the initial context, the processing status is restored from the state information, and the stream of processing instructions is continued.

公开(公告)号：US11948069B2

公开(公告)日：2024-04-02

申请号：US16518444

申请日：2019-07-22

Applicant: Arm Limited

Inventor： Lingchuan Meng ,  John Wakefield Brothers, III ,  Jens Olson ,  Jared Corey Smolens ,  Eric Kunze ,  Ian Rudolf Bratt

IPC: G06N3/063 ,  H03M7/30

CPC classification number: G06N3/063 ,  H03M7/70

Abstract: A processor arranged to compress neural network activation data comprising an input module for obtaining neural network activation data. The processor also comprises a block creation module arranged to split the neural network activation data into a plurality of blocks; and a metadata generation module for generating metadata associated with at least one of the plurality of blocks. Based on the metadata generated a selection module selects a compression scheme for each of the plurality of blocks, and a compression module for applying the selected compression scheme to the corresponding block to produce compressed neural network activation data. An output module is also provided for outputting the compressed neural network activation data.

公开(公告)号：US11892972B2

公开(公告)日：2024-02-06

申请号：US17469311

申请日：2021-09-08

Applicant: Apical Limited ,  Arm Limited

Inventor： Aaron Debattista ,  Jared Corey Smolens

IPC: G06F15/82 ,  G06F9/48 ,  G06F9/52 ,  G06F8/41 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F15/82 ,  G06F8/458 ,  G06F9/30087 ,  G06F9/3851 ,  G06F9/4881 ,  G06F9/526

Abstract: Systems, apparatuses and methods suitable for optimizing synchronization mechanisms for multi-core processors are provided. The synchronizing mechanisms may be optimized by receiving a command stream which comprises a plurality of commands including one or more wait commands, wherein each wait command has an associated state and one or more associated conditions; sequentially processing each command in the command stream until a wait command is reached; checking the state associated with the wait command to be processed, wherein if said state is a blocking state, further processing of commands in the command stream is paused until each of said wait command's associated conditions are met, and wherein if said state is a non-blocking state, the next command in the command stream is retrieved and processed.