公开(公告)号：US11226828B2

公开(公告)日：2022-01-18

申请号：US16376058

申请日：2019-04-05

Applicant: Arm Limited

Inventor： Peter Vrabel ,  Allan John Skillman

IPC: G06F9/4401 ,  G06F1/08 ,  G06F9/48 ,  G06F1/3296

Abstract: Apparatuses comprising data processing circuitry and a wakeup interrupt controller and methods of operating the apparatuses are disclosed. Prior to the processing circuitry entering a low power state, indications of pending interrupts are transferred to the wakeup interrupt controller. Further indications of interrupts received whilst the processing circuitry is in the low power state may be accumulated in the wakeup interrupt controller. When the wakeup interrupt controller receives a wakeup signal, the indications of pending interrupts are transferred to the processing circuitry and the processing circuitry exits the low power state.

公开(公告)号：US11281473B2

公开(公告)日：2022-03-22

申请号：US16376075

申请日：2019-04-05

Applicant: Arm Limited

Inventor： Peter Vrabel

IPC: G06F1/32 ,  G06F9/4401 ,  G06F1/3296 ,  G06F1/28 ,  G06F1/08 ,  G06F9/48 ,  G06F1/3287 ,  G06F1/3234

Abstract: Apparatuses comprising processing circuitry, a first wakeup interrupt controller connected to the processing circuitry via a first interface, and a second wakeup interrupt controller connected to the processing circuitry via a second interface, and methods of operating such apparatuses, are disclosed. Prior to the processing circuitry entering a low power state, information defining at least one wakeup event is transferred from the processing circuitry to a selected wakeup interrupt controller. Whilst the processing circuitry is in the low power state, the selected wakeup interrupt controller receives event indications. If one of these event indications is a defined wakeup event, then the processing circuitry is caused to exit the low power state.

公开(公告)号：US11210186B2

公开(公告)日：2021-12-28

申请号：US16295226

申请日：2019-03-07

Applicant: Arm Limited

Inventor： Peter Vrabel ,  Alan Jeremy Becker

IPC: G06F11/00 ,  G06F11/20 ,  G06F11/14 ,  G06F12/02 ,  G06F12/0897 ,  G06F11/10 ,  G06F12/0817

Abstract: An apparatus comprises a non-associative memory comprising a plurality of storage locations, and error recovery storage to store at least one error recovery entry providing a recovery value for a corresponding storage location of the non-associative memory. Control circuitry is responsive to a non-associative memory read request specifying a target address of a storage location of the non-associative memory, when the error recovery storage includes a valid matching error recovery entry for which the corresponding storage location is the storage location identified by the target address, to return the recovery value stored in the valid matching error recovery entry as a response to the non-associative memory read request, instead of information stored in the storage location identified by the target address. This enables the apparatus to continue to function even if hard errors occur in a storage location of the non-associative memory.