公开(公告)号：US08848412B1

公开(公告)日：2014-09-30

申请号：US13935710

申请日：2013-07-05

Applicant: Arm Limited

Inventor： Gus Yeung ,  Yew Keong Chong ,  Wang-Kun Chen

IPC: G11C15/00 ,  G11C11/56 ,  G11C15/04

CPC classification number: G11C15/00 ,  G11C11/56 ,  G11C15/04

Abstract: A ternary content addressable memory (TCAM) has at least one TCAM cell comprising first and second memory bitcells for storing first and second bit values representing a cell state comprising one of a first cell state, a second cell state and a mask cell state. The first and second memory bitcells share a pair of bitlines for accessing the first and second bit values. Access control circuitry is provided for triggering, in response to a clock signal, a read or write access to the first memory bitcell during a first portion of a clock cycle and triggering a read access or write access to the second read bitcell during a second portion of the clock cycle.

Abstract translation: 三元内容可寻址存储器（TCAM）具有至少一个TCAM单元，其包括用于存储表示包括第一单元状态，第二单元状态和掩码单元状态之一的单元状态的第一和第二位值的第一和第二存储器位单元。 第一和第二存储器位单元共享用于访问第一和第二位值的一对位线。 提供访问控制电路，用于在时钟周期的第一部分期间响应于时钟信号触发对第一存储器位单元的读或写访问，并且在第二部分期间触发对第二读位元的读访问或写访问 的时钟周期。

公开(公告)号：US09111596B2

公开(公告)日：2015-08-18

申请号：US13967908

申请日：2013-08-15

Applicant: ARM Limited

Inventor： Sriram Thyagarajan ,  Yew Keong Chong ,  Wang-Kun Chen ,  Gus Yeung

IPC: G11C7/10 ,  G11C8/08 ,  G11C8/06

CPC classification number: G11C8/08 ,  G11C7/10 ,  G11C8/06

Abstract: A memory device comprises an array of bitcells arranged as a plurality of rows of bitcells and a plurality of columns of bitcells, and has a plurality of wordlines and a plurality of readout channels. A control unit is configured to control access to the array of bitcells, wherein in response to a memory access request specifying a memory address the control unit is configured to activate a selected wordline and to activate the plurality of readout channels, and to access a row of bitcells in said array storing a data word and addressed by the memory address. The data word consists of a number of data bits given by a number of bitcells in each row of bitcells. The control unit is further configured to be responsive to a masking signal and, when the masking signal is asserted when said memory access request is received, the control unit is configured to activate only a portion of the selected wordline and a portion of the plurality of readout channels, such that only a portion of the data word is accessed.

Abstract translation: 存储器件包括排列成多行比特单元和多列比特单元的位单元阵列，并且具有多个字线和多个读出通道。 控制单元被配置为控制对位单元阵列的访问，其中响应于指定存储器地址的存储器访问请求，控制单元被配置为激活所选择的字线并激活多个读出通道，并且访问行 所述阵列中的位单元存储数据字并由存储器地址寻址。 数据字由每行位单元中的多个位单元给出的多个数据位组成。 所述控制单元还被配置为响应于屏蔽信号，并且当接收到所述存储器访问请求时屏蔽信号被断言时，所述控制单元被配置为仅激活所选字线的一部分和所述多个 读出通道，使得仅访问数据字的一部分。

公开(公告)号：US20150049568A1

公开(公告)日：2015-02-19

申请号：US13967908

申请日：2013-08-15

Applicant: ARM Limited

Inventor： Sriram Thyagarajan ,  Yew Keong Chong ,  Wang-Kun Chen ,  Gus Yeung

IPC: G11C8/00

CPC classification number: G11C8/08 ,  G11C7/10 ,  G11C8/06

Abstract: A memory device comprises an array of bitcells arranged as a plurality of rows of bitcells and a plurality of columns of bitcells, and has a plurality of wordlines and a plurality of readout channels. A control unit is configured to control access to the array of bitcells, wherein in response to a memory access request specifying a memory address the control unit is configured to activate a selected wordline and to activate the plurality of readout channels, and to access a row of bitcells in said array storing a data word and addressed by the memory address. The data word consists of a number of data bits given by a number of bitcells in each row of bitcells. The control unit is further configured to be responsive to a masking signal and, when the masking signal is asserted when said memory access request is received, the control unit is configured to activate only a portion of the selected wordline and a portion of the plurality of readout channels, such that only a portion of the data word is accessed.

Abstract translation: 存储器件包括排列成多行比特单元和多列比特单元的位单元阵列，并且具有多个字线和多个读出通道。 控制单元被配置为控制对位单元阵列的访问，其中响应于指定存储器地址的存储器访问请求，控制单元被配置为激活所选择的字线并激活多个读出通道，并且访问行 所述阵列中的位单元存储数据字并由存储器地址寻址。 数据字由每行位单元中的多个位单元给出的多个数据位组成。 所述控制单元还被配置为响应于屏蔽信号，并且当接收到所述存储器访问请求时屏蔽信号被断言时，所述控制单元被配置为仅激活所选字线的一部分和所述多个 读出通道，使得仅访问数据字的一部分。

公开(公告)号：US08947968B2

公开(公告)日：2015-02-03

申请号：US13936512

申请日：2013-07-08

Applicant: ARM Limited

Inventor： Wang-Kun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Gus Yeung

IPC: G11C7/00 ,  G11C5/14

CPC classification number: G11C11/417 ,  G11C5/148

Abstract: A memory has a normal mode and a power saving mode. The memory has bitline precharge circuitry which during the normal mode selectively couples a pair of bitlines to a precharge node to charge the bitlines to a given voltage level. During the power saving mode the bitlines are isolated from the precharge node. Voltage control circuitry is provided to maintain the precharge node at a first voltage level during the normal mode and at a second voltage level less than the first voltage level during the power saving mode. By reducing the voltage level at the precharge node during the power saving mode, the amount of inrush current occurring when switching from power saving mode to normal mode can be reduced, and this enables the wakeup time to be reduced when returning from power saving mode to normal mode.

Abstract translation: 存储器具有正常模式和省电模式。 存储器具有位线预充电电路，其在正常模式期间选择性地将一对位线耦合到预充电节点，以将位线充电到给定的电压电平。 在省电模式期间，位线与预充电节点隔离。 提供电压控制电路以在正常模式期间将预充电节点保持在第一电压电平，并且在省电模式期间处于小于第一电压电平的第二电压电平。 通过在省电模式下减小预充电节点处的电压电平，可以减少从省电模式切换到正常模式时所产生的浪涌电流量，并且能够在从省电模式返回时减少唤醒时间 正常模式。