公开(公告)号：US08650748B2

公开(公告)日：2014-02-18

申请号：US13106383

申请日：2011-05-12

申请人： Artur Darbinyan ,  David T. Chin ,  Kurt E. Sincerbox

发明人： Artur Darbinyan ,  David T. Chin ,  Kurt E. Sincerbox

IPC分类号： H05K3/30

CPC分类号： H01L21/486 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/181 ,  H05K3/4046 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49789 ,  Y10T29/49798 ,  Y10T29/53174 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of fabricating chip carriers suitable for use in packaging integrated circuits and other electronic, electro-mechanical and opto-electronic devices is described. In general, a number of wires (or wires and rods) are arranged in parallel in a wiring fixture. After the wires are positioned, they are encapsulated to form an encapsulated wiring block. The wiring block is then sliced to form a number of discrete panels. Preferably, the various wires are geometrically positioned such that each resulting panel has a large number of device areas defined therein. The encapsulant in each panel effectively forms a substrate and the wire segments in each panel form conductive vias that extend through the substrate. The resulting panels/chip carriers can then be used in a wide variety of packaging applications.

摘要翻译： 描述了适用于封装集成电路和其他电子，机电和光电子器件的芯片载体的制造方法。 通常，在配线夹具中并列布置有多根线（或线和杆）。 电线定位后，将其封装形成封装的接线块。 然后将接线块切片以形成多个离散面板。 优选地，各种导线几何地定位成使得每个所得到的面板具有限定在其中的大量设备区域。 每个面板中的密封剂有效地形成衬底，并且每个面板中的线段形成延伸穿过衬底的导电通路。 所得到的面板/芯片载体然后可用于各种各样的包装应用中。