Semiconductor device having cavities with submicrometer dimensions generated by a swelling process
    4.
    发明授权
    Semiconductor device having cavities with submicrometer dimensions generated by a swelling process 有权
    具有通过膨胀过程产生亚微米尺寸的腔的半导体器件

    公开(公告)号:US06645850B2

    公开(公告)日:2003-11-11

    申请号:US10230753

    申请日:2002-08-29

    IPC分类号: H01L214763

    摘要: A method creates structured cavities with submicrometer dimensions in a cavity layer of a semiconductor device. A processing material that incorporates a swelling agent is deposited on ridges of a working layer that is constructed of ridges and trenches. The processing material expands over the trenches during swelling; and covered cavities thus emerge from the trenches.

    摘要翻译: 一种方法在半导体器件的空腔层中产生具有亚微米尺寸的结构化空腔。 掺有溶胀剂的处理材料沉积在由脊和沟构成的工作层的脊上。 处理材料在膨胀期间在沟槽上膨胀; 并且覆盖的空腔因此从沟槽中出现。

    Condensed memory cell structure using a FinFET
    8.
    发明授权
    Condensed memory cell structure using a FinFET 有权
    使用FinFET的冷凝存储单元结构

    公开(公告)号:US08665629B2

    公开(公告)日:2014-03-04

    申请号:US11864575

    申请日:2007-09-28

    IPC分类号: G11C11/00

    摘要: An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell that includes a resistivity changing memory element. The resistivity changing memory element is electrically coupled to a select transistor that includes a FinFET including a source, a drain, and a fin structure formed above a surface of a substrate between the source and the drain. The fin structure includes a channel area extending in a direction substantially parallel to the surface of the substrate, and a dielectric layer formed around at least a portion of the channel area such that an effective channel width of the select transistor depends at least in part on a height of the fin structure.

    摘要翻译: 对集成电路的集成电路及其制造方法进行说明。 在一个实施例中,集成电路包括包括电阻率变化存储元件的存储单元。 电阻率变化存储元件电耦合到选择晶体管,该选择晶体管包括在源极和漏极之间形成在衬底表面上方的源极,漏极和鳍状结构的FinFET。 翅片结构包括在基本上平行于衬底的表面的方向上延伸的沟道区,以及围绕沟道区的至少一部分形成的介电层,使得选择晶体管的有效沟道宽度至少部分依赖于 翅片结构的高度。

    Integrated circuit, method of manufacturing an integrated circuit, and memory module
    10.
    发明授权
    Integrated circuit, method of manufacturing an integrated circuit, and memory module 有权
    集成电路,集成电路的制造方法和存储器模块

    公开(公告)号:US07855435B2

    公开(公告)日:2010-12-21

    申请号:US12047167

    申请日:2008-03-12

    IPC分类号: H01L23/48

    摘要: According to one embodiment of the present invention, an integrated circuit including a plurality of memory cells is provided. Each memory cell includes a resistivity changing memory element which includes a top electrode, a bottom electrode, and resistivity changing material being disposed between the top electrode and the bottom electrode. Each resistivity changing memory element is at least partially surrounded by a thermal insulating structure. The thermal insulating structures are arranged such that the dissipation of heat generated within the resistivity changing memory elements into the environment of the resistivity changing memory elements is lowered.

    摘要翻译: 根据本发明的一个实施例,提供了包括多个存储单元的集成电路。 每个存储单元包括电阻率变化存储元件,其包括设置在顶部电极和底部电极之间的顶部电极,底部电极和电阻率变化材料。 每个电阻率变化记忆元件至少部分地被绝热结构包围。 热绝缘结构被布置成使得在电阻率变化的存储元件内产生的热量消耗到电阻率变化存储元件的环境中降低。