Semiconductor device manufacturing methods
    5.
    发明授权
    Semiconductor device manufacturing methods 有权
    半导体器件制造方法

    公开(公告)号:US08697339B2

    公开(公告)日:2014-04-15

    申请号:US13081377

    申请日:2011-04-06

    IPC分类号: G03F7/20

    摘要: Methods for manufacturing semiconductor devices are disclosed. One preferred embodiment is a method of processing a semiconductor device. The method includes providing a workpiece having a material layer to be patterned disposed thereon. A masking material is formed over the material layer of the workpiece. The masking material includes a lower portion and an upper portion disposed over the lower portion. The upper portion of the masking material is patterned with a first pattern. A polymer material is disposed over the masking material. The masking material and the polymer layer are used to pattern the material layer of the workpiece.

    摘要翻译: 公开了制造半导体器件的方法。 一个优选实施例是一种处理半导体器件的方法。 该方法包括提供具有设置在其上的待图案化材料层的工件。 在工件的材料层上形成掩模材料。 掩模材料包括下部和设置在下部上的上部。 用第一图案对掩模材料的上部进行图案化。 聚合物材料设置在掩蔽材料上方。 掩模材料和聚合物层用于对工件的材料层进行图案化。

    Semiconductor Devices and Methods of Manufacturing Thereof
    6.
    发明申请
    Semiconductor Devices and Methods of Manufacturing Thereof 有权
    半导体器件及其制造方法

    公开(公告)号:US20110250530A1

    公开(公告)日:2011-10-13

    申请号:US13164139

    申请日:2011-06-20

    IPC分类号: G03F1/00 G06F17/50

    摘要: Semiconductor devices and methods of manufacturing thereof are disclosed. A plurality of features is formed on a workpiece, the plurality of features being located in a first region and a second region of the workpiece. Features in the first region have a first lateral dimension, and features in the second region have a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension. The first region is masked, and the second lateral dimension of features in the second region is reduced.

    摘要翻译: 公开了半导体器件及其制造方法。 多个特征形成在工件上,多个特征位于工件的第一区域和第二区域中。 第一区域中的特征具有第一横向尺寸,并且第二区域中的特征具有第二横向尺寸,其中第二横向尺寸大于第一横向尺寸。 第一区域被掩蔽,并且第二区域中的特征的第二横向尺寸减小。

    Method for Manufacturing a Semiconductor Device Having Doped and Undoped Polysilicon Layers
    7.
    发明申请
    Method for Manufacturing a Semiconductor Device Having Doped and Undoped Polysilicon Layers 有权
    具有掺杂和未掺杂多晶硅层的半导体器件的制造方法

    公开(公告)号:US20110031563A1

    公开(公告)日:2011-02-10

    申请号:US12910239

    申请日:2010-10-22

    IPC分类号: H01L29/49

    摘要: Various illustrative embodiments of methods for manufacturing a semiconductor device are described. These methods may include, for example, forming a first polysilicon layer above a substrate, wherein the first polysilicon layer comprises a doped portion, and forming a second polysilicon layer over a surface of the first polysilicon layer. Also, various illustrative embodiments of semiconductor devices are described that may be manufactured such as by the various methods described herein.

    摘要翻译: 描述用于制造半导体器件的方法的各种说明性实施例。 这些方法可以包括例如在衬底上形成第一多晶硅层,其中第一多晶硅层包括掺杂部分,并且在第一多晶硅层的表面上形成第二多晶硅层。 而且,描述了半导体器件的各种说明性实施例,其可以通过本文所述的各种方法来制造。

    Threshold Voltage Consistency and Effective Width in Same-Substrate Device Groups
    8.
    发明申请
    Threshold Voltage Consistency and Effective Width in Same-Substrate Device Groups 有权
    相同基板设备组中的阈值电压一致性和有效宽度

    公开(公告)号:US20090227086A1

    公开(公告)日:2009-09-10

    申请号:US12043384

    申请日:2008-03-06

    IPC分类号: H01L21/76

    CPC分类号: H01L21/76262 H01L21/76278

    摘要: The prevention of active area loss in the STI model is disclosed which results in an improved device performance in devices manufactured according to the process flow. The process generally shared among the multiple various embodiments inverts the current conventional STI structure towards a process flow where an insulator is patterned with tapered trenches. A segregation layer is formed beneath the surface of the insulator in the tapered trenches. The tapered trenches are then filled with a semiconductor material which is further processed to create a number of active devices. Therefore, the active devices are created in patterned dielectric instead of the STI being created in the semiconductor substrate of the active devices.

    摘要翻译: 公开了STI模型中的有源面积损耗的防止,这导致根据工艺流程制造的器件中的器件性能提高。 多个不同实施例中通常共享的方法将当前常规STI结构转换为绝缘体用锥形图案化的工艺流程。 在锥形沟槽中的绝缘体的表面下方形成偏析层。 然后用半导体材料填充锥形沟槽,半导体材料被进一步处理以产生多个有源器件。 因此,有源器件是在图案化电介质中产生的,而不是在有源器件的半导体衬底中产生的STI。

    Feature Dimension Control in a Manufacturing Process
    9.
    发明申请
    Feature Dimension Control in a Manufacturing Process 审中-公开
    制造过程中的特征尺寸控制

    公开(公告)号:US20100120177A1

    公开(公告)日:2010-05-13

    申请号:US12691218

    申请日:2010-01-21

    CPC分类号: H01L21/32137 H01L22/12

    摘要: A method for manufacturing a semiconductor device is disclosed including determining a dimension or other physical characteristic of a pattern in a layer of material that is disposed on a workpiece, and etching the layer of material using information that is related to the dimension. A system is also disclosed for manufacturing a semiconductor device including a first etch system configured to etch a layer to define a pattern in the layer, and a second etch system configured to measure a physical characteristic of the pattern, determine an etch control parameter based on the physical characteristic, and etch the layer in accordance with the etch control parameter.

    摘要翻译: 公开了一种用于制造半导体器件的方法,其包括确定设置在工件上的材料层中的图案的尺寸或其他物理特性,以及使用与所述尺寸相关的信息来蚀刻所述材料层。 还公开了一种用于制造半导体器件的系统,该半导体器件包括被配置为蚀刻层以限定该层中的图案的第一蚀刻系统,以及被配置为测量该图案的物理特性的第二蚀刻系统,基于 物理特性,并根据蚀刻控制参数刻蚀该层。

    Semiconductor device manufacturing methods
    10.
    发明申请
    Semiconductor device manufacturing methods 审中-公开
    半导体器件制造方法

    公开(公告)号:US20080286698A1

    公开(公告)日:2008-11-20

    申请号:US11804528

    申请日:2007-05-18

    IPC分类号: H01L21/02 G03C5/00

    摘要: Methods for manufacturing semiconductor devices are disclosed. One preferred embodiment is a method of processing a semiconductor device. The method includes providing a workpiece having a material layer to be patterned disposed thereon. A masking material is formed over the material layer of the workpiece. The masking material includes a lower portion and an upper portion disposed over the lower portion. The upper portion of the masking material is patterned with a first pattern. An additional substance is introduced and the lower portion of the masking material is patterned. The masking material and the additional substance are used to pattern the material layer of the workpiece.

    摘要翻译: 公开了制造半导体器件的方法。 一个优选实施例是一种处理半导体器件的方法。 该方法包括提供具有设置在其上的待图案化材料层的工件。 在工件的材料层上形成掩模材料。 掩模材料包括下部和设置在下部上的上部。 用第一图案对掩模材料的上部进行图案化。 引入另外的物质,掩模材料的下部被图案化。 掩模材料和附加物质用于对工件的材料层进行图案化。