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公开(公告)号：US08027213B2
公开(公告)日：2011-09-27
申请号：US12488121
申请日：2009-06-19
IPC分类号： G11C7/00
CPC分类号： G11C11/413 , G11C11/41 , G11C29/48 , G11C29/50 , G11C29/50012 , G11C2029/5006
摘要： A mechanism for measuring the variability of the read current of SRAM cells on an integrated circuit includes the integrated circuit having an SRAM array including a plurality of SRAM cells. The integrated circuit may also include a selection circuit configured to select a particular SRAM cell in response to a selection input. An oscillator circuit such as a ring oscillator, for example, on the integrated circuit may be configured to oscillate at a frequency that is dependent upon a read current of a selected SRAM cell during operation in a first mode. A frequency determining circuit that is coupled to the oscillator circuit may be configured to output a value corresponding to the frequency of oscillation of the oscillator circuit.
摘要翻译： 用于测量集成电路上的SRAM单元的读取电流的可变性的机构包括具有包括多个SRAM单元的SRAM阵列的集成电路。 集成电路还可以包括被配置为响应于选择输入来选择特定SRAM单元的选择电路。 例如集成电路上的诸如环形振荡器的振荡器电路可被配置为以在第一模式下操作期间取决于所选择的SRAM单元的读取电流的频率进行振荡。 耦合到振荡器电路的频率确定电路可以被配置为输出与振荡器电路的振荡频率相对应的值。
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公开(公告)号：US20100322026A1
公开(公告)日：2010-12-23
申请号：US12488121
申请日：2009-06-19
CPC分类号： G11C11/413 , G11C11/41 , G11C29/48 , G11C29/50 , G11C29/50012 , G11C2029/5006
摘要： A mechanism for measuring the variability of the read current of SRAM cells on an integrated circuit includes the integrated circuit having an SRAM array including a plurality of SRAM cells. The integrated circuit may also include a selection circuit configured to select a particular SRAM cell in response to a selection input. An oscillator circuit such as a ring oscillator, for example, on the integrated circuit may be configured to oscillate at a frequency that is dependent upon a read current of a selected SRAM cell during operation in a first mode. A frequency determining circuit that is coupled to the oscillator circuit may be configured to output a value corresponding to the frequency of oscillation of the oscillator circuit.
摘要翻译： 用于测量集成电路上的SRAM单元的读取电流的可变性的机构包括具有包括多个SRAM单元的SRAM阵列的集成电路。 集成电路还可以包括被配置为响应于选择输入来选择特定SRAM单元的选择电路。 例如集成电路上的诸如环形振荡器的振荡器电路可被配置为以在第一模式下操作期间取决于所选择的SRAM单元的读取电流的频率进行振荡。 耦合到振荡器电路的频率确定电路可以被配置为输出与振荡器电路的振荡频率相对应的值。
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3.发明授权Apparatus and method for testing level shifter voltage thresholds on an integrated circuit 有权在集成电路上测试电平移位器电压阈值的装置和方法公开(公告)号：US07977998B2
公开(公告)日：2011-07-12
申请号：US12481253
申请日：2009-06-09
IPC分类号： H03L5/00
CPC分类号： H03K19/018507 , G01R31/318555 , G01R31/318572
摘要： An apparatus and method for testing level shifter threshold voltages on an integrated circuit includes one or more level shifter modules each including a number of level shifter circuits. Each level shifter circuit may be coupled to a first and a second voltage supply. Each level shifter circuit may also receive an input signal that is referenced to the first voltage supply, and to generate an output signal that is referenced to the second voltage supply. In addition, each level shifter module may include detection logic that may detect an output value of each of the level shifter circuits. The control circuit may be configured to iteratively change the voltage output from one of the voltage supplies, and maintaining a voltage on the other voltage supply while the input signal is provided to the level shifter circuits. The detection logic may capture the output value upon each change in voltage.
摘要翻译： 用于在集成电路上测试电平移位器阈值电压的装置和方法包括一个或多个电平移位器模块，每个电平移位器模块包括多个电平移位器电路。 每个电平移位器电路可以耦合到第一和第二电压源。 每个电平移位器电路还可以接收参考第一电压源的输入信号，并产生参考第二电压源的输出信号。 此外，每个电平移位器模块可以包括可以检测每个电平移位器电路的输出值的检测逻辑。 控制电路可以被配置为迭代地改变来自一个电压源的电压输出，并且在输入信号被提供给电平移位器电路的同时保持另一个电压源上的电压。 检测逻辑可以在每次电压变化时捕获输出值。
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4.发明申请APPARATUS AND METHOD FOR TESTING LEVEL SHIFTER VOLTAGE THRESHOLDS ON AN INTEGRATED CIRCUIT 有权在集成电路上测试水平变压器电压的装置和方法公开(公告)号：US20100308887A1
公开(公告)日：2010-12-09
申请号：US12481253
申请日：2009-06-09
IPC分类号： H03L5/00
CPC分类号： H03K19/018507 , G01R31/318555 , G01R31/318572
摘要： An apparatus and method for testing level shifter threshold voltages on an integrated circuit includes one or more level shifter modules each including a number of level shifter circuits. Each level shifter circuit may be coupled to a first and a second voltage supply. Each level shifter circuit may also receive an input signal that is referenced to the first voltage supply, and to generate an output signal that is referenced to the second voltage supply. In addition, each level shifter module may include detection logic that may detect an output value of each of the level shifter circuits. The control circuit may be configured to iteratively change the voltage output from one of the voltage supplies, and maintaining a voltage on the other voltage supply while the input signal is provided to the level shifter circuits. The detection logic may capture the output value upon each change in voltage.
摘要翻译： 用于在集成电路上测试电平移位器阈值电压的装置和方法包括一个或多个电平移位器模块，每个电平移位器模块包括多个电平移位器电路。 每个电平移位器电路可以耦合到第一和第二电压源。 每个电平移位器电路还可以接收参考第一电压源的输入信号，并产生参考第二电压源的输出信号。 此外，每个电平移位器模块可以包括可以检测每个电平移位器电路的输出值的检测逻辑。 控制电路可以被配置为迭代地改变来自一个电压源的电压输出，并且在输入信号被提供给电平移位器电路的同时保持另一个电压源上的电压。 检测逻辑可以在每次电压变化时捕获输出值。
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公开(公告)号：US07454674B2
公开(公告)日：2008-11-18
申请号：US11325123
申请日：2006-01-04
IPC分类号： G01R31/28
CPC分类号： G01R31/31709
摘要： In one embodiment, a jitter detector comprises a logic circuit coupled to receive a plurality of inputs indicative of states captured from a plurality of outputs of a delay chain responsive to a first clock input and a plurality of clocked storage devices coupled to the logic circuit. The logic circuit is configured to identify a first input of the plurality of inputs that is: (i) captured in error from a corresponding one of the plurality of outputs of the delay chain, and (ii) the corresponding one of the plurality of outputs of the delay chain is least delayed by the delay chain among the plurality of outputs that are captured in error. The plurality of clocked storage devices are configured to accumulate an indication of which of the plurality of outputs have been captured in error over a plurality of clock cycles of the first clock input.
摘要翻译： 在一个实施例中，抖动检测器包括逻辑电路，其被耦合以响应于第一时钟输入和耦合到逻辑电路的多个时钟存储装置接收指示从延迟链的多个输出捕获的状态的多个输入。 所述逻辑电路被配置为识别所述多个输入的第一输入，所述第一输入是：（i）从所述延迟链的所述多个输出中的相应一个输出中错误地捕获，以及（ii）所述多个输出中的相应一个输出 延迟链的延迟链在由误差捕获的多个输出之中延迟链最小延迟。 多个时钟存储装置被配置为在第一时钟输入的多个时钟周期上累积已经捕获了多个输出中的哪一个的指示。
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6.发明授权Digital leakage detector that detects transistor leakage current in an integrated circuit 有权数字泄漏检测器，用于检测集成电路中的晶体管漏电流公开(公告)号：US07411409B2
公开(公告)日：2008-08-12
申请号：US11281110
申请日：2005-11-17
IPC分类号： G01R31/26
CPC分类号： G01R31/025
摘要： In one embodiment, an integrated circuit includes at least one digital leakage detector that includes digital circuitry configured to detect an approximation of a magnitude of the leakage current in transistors of the integrated circuit and configured to generate a digital output representing the approximated magnitude. In another embodiment, a leak detector includes leak circuits and clocked storage devices. Each leak circuit is configured to generate an output signal indicative of a different magnitude of leakage current in a transistor. The clocked storage devices are configured to capture a state representing the output signals of the leak circuits. In another embodiment, a method includes running a test for leakage current in a digital leakage detector, wherein a digital output of the digital leakage detector represents a magnitude of a leakage current being experienced by the integrated circuit during use; and outputting the digital output from the integrated circuit.
摘要翻译： 在一个实施例中，集成电路包括至少一个数字泄漏检测器，其包括被配置为检测集成电路的晶体管中的漏电流的大小近似的数字电路，并被配置为产生表示近似量值的数字输出。 在另一个实施例中，泄漏检测器包括泄漏电路和时钟存储装置。 每个泄漏电路被配置为产生指示晶体管中的不同大小的漏电流的输出信号。 时钟存储设备被配置为捕获表示泄漏电路的输出信号的状态。 在另一个实施例中，一种方法包括对数字泄漏检测器中的漏电流进行测试，其中数字泄漏检测器的数字输出表示集成电路在使用过程中经历的漏电流的大小; 并从集成电路输出数字输出。
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7.发明授权Apparatus and method for testing driver writeability strength on an integrated circuit 有权在集成电路上测试驱动器可写性强度的装置和方法公开(公告)号：US08947070B2
公开(公告)日：2015-02-03
申请号：US13351313
申请日：2012-01-17
申请人： Ashish R. Jain , Edgardo F. Klass
发明人： Ashish R. Jain , Edgardo F. Klass
IPC分类号： G11C8/00 , G01R31/3185 , G01R31/319
CPC分类号： G01R31/318572 , G01R31/31924
摘要： An apparatus and method for testing driver write-ability strength on an integrated circuit includes one or more drive detection units each including a number of drivers. At least some of the drivers may have a different drive strength and each may drive a voltage onto a respective driver output line. Each drive detection unit may include a number of keeper circuits, each coupled to a separate output line and configured to retain a given voltage on the output line to which it is coupled. Each detection unit may also include a number of detection circuits coupled to detect the drive voltage on each of the output lines. In one implementation, the drive voltage appearing at the output line of each driver may be indicative of that the driver was able to overdrive the voltage being retained on the output line to which it is coupled by the respective keeper circuits.
摘要翻译： 用于在集成电路上测试驱动器写入能力强度的装置和方法包括一个或多个驱动器检测单元，每个驱动器检测单元包括多个驱动器。 至少一些驱动器可能具有不同的驱动强度，并且每个驱动器可以将电压驱动到相应的驱动器输出线上。 每个驱动器检测单元可以包括多个保持器电路，每个保持器电路分别耦合到单独的输出线并被配置为将给定电压保持在与其耦合的输出线上。 每个检测单元还可以包括多个检测电路，其被耦合以检测每条输出线上的驱动电压。 在一个实施方案中，出现在每个驱动器的输出线处的驱动电压可以指示驾驶员能够过度驱动保持在由相应保持器电路耦合到的输出线上的电压。
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8.发明授权Apparatus and method for testing driver writeability strength on an integrated circuit 有权在集成电路上测试驱动器可写性强度的装置和方法公开(公告)号：US08125211B2
公开(公告)日：2012-02-28
申请号：US12481265
申请日：2009-06-09
申请人： Ashish R. Jain , Edgardo F. Klass
发明人： Ashish R. Jain , Edgardo F. Klass
CPC分类号： G01R31/318572 , G01R31/31924
摘要： An apparatus and method for testing driver write-ability strength on an integrated circuit includes one or more drive detection units each including a number of drivers. At least some of the drivers may have a different drive strength and each may drive a voltage onto a respective driver output line. Each drive detection unit may include a number of keeper circuits, each coupled to a separate output line and configured to retain a given voltage on the output line to which it is coupled. Each detection unit may also include a number of detection circuits coupled to detect the drive voltage on each of the output lines. In one implementation, the drive voltage appearing at the output line of each driver may be indicative of that the driver was able to overdrive the voltage being retained on the output line to which it is coupled by the respective keeper circuits.
摘要翻译： 用于在集成电路上测试驱动器写入能力强度的装置和方法包括一个或多个驱动器检测单元，每个驱动器检测单元包括多个驱动器。 至少一些驱动器可能具有不同的驱动强度，并且每个驱动器可以将电压驱动到相应的驱动器输出线上。 每个驱动器检测单元可以包括多个保持器电路，每个保持器电路分别耦合到单独的输出线并被配置为将给定电压保持在与其耦合的输出线上。 每个检测单元还可以包括多个检测电路，其被耦合以检测每条输出线上的驱动电压。 在一个实施方案中，出现在每个驱动器的输出线处的驱动电压可以指示驾驶员能够过度驱动保持在由相应保持器电路耦合到的输出线上的电压。
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9.发明授权Apparatus and method for testing sense amplifier thresholds on an integrated circuit 有权在集成电路上测试读出放大器阈值的装置和方法公开(公告)号：US08154275B2
公开(公告)日：2012-04-10
申请号：US12503315
申请日：2009-07-15
申请人： Ashish R. Jain , Edgardo F. Klass
发明人： Ashish R. Jain , Edgardo F. Klass
CPC分类号： G11C29/02 , G11C29/026 , G11C29/12005
摘要： An apparatus and method for testing sense amplifier threshold voltages on an integrated circuit includes one or more sense amplifier modules each including a number of sense amplifier circuits, a voltage generator unit, and detection logic. The voltage generator unit may select a differential voltage to supply to at least some of the sense amplifier circuits, and each sense amplifier circuit may be configured to generate an output value that is dependent upon the applied differential voltage in response to receiving an enable signal. The detection logic may detect and capture an output value of each of the sense amplifier circuits. In one implementation, the voltage generator unit may iteratively select a different differential voltage in response to a control input. Accordingly, the detection logic may capture the output value of the sense amplifiers after each change in differential voltage.
摘要翻译： 用于测试集成电路上的读出放大器阈值电压的装置和方法包括一个或多个感测放大器模块，每个读出放大器模块包括多个读出放大器电路，电压发生器单元和检测逻辑。 电压发生器单元可以选择差分电压以供应至少一些读出放大器电路，并且每个读出放大器电路可以被配置为响应于接收使能信号而产生取决于施加的差分电压的输出值。 检测逻辑可以检测和捕获每个读出放大器电路的输出值。 在一个实现中，电压发生器单元可以响应于控制输入而迭代地选择不同的差分电压。 因此，检测逻辑可以在差分电压的每次改变之后捕获读出放大器的输出值。
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公开(公告)号：US20110202809A1
公开(公告)日：2011-08-18
申请号：US12705839
申请日：2010-02-15
申请人： Edgardo F. Klass , Ashish R. Jain
发明人： Edgardo F. Klass , Ashish R. Jain
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318541
摘要： In an embodiment, a clocked storage device such as a pulse flop is provided. The pulse flop includes a latch coupled to receive a scan data input to the pulse flop. The latch receives the scan data input during one of the phases of the clock, and retains the received input during the other phase. The other phase is the phase in which the pulse to the pulse flop occurs. Thus, when scan data is captured in the pulse flop, the latch at the next pulse flop in the chain may be closed and may prevent a race condition in propagating the scan data.
摘要翻译： 在一个实施例中，提供了诸如脉冲触发器的计时存储装置。 所述脉冲触发器包括耦合以接收输入到所述脉冲触发器的扫描数据的锁存器。 锁存器在时钟的一个相位期间接收扫描数据输入，并在另一阶段期间保持所接收的输入。 另一相是产生脉冲触发脉冲的相位。 因此，当在脉冲触发器中捕获扫描数据时，链中下一个脉冲触发器处的锁存器可能被关闭，并且可以防止传播扫描数据时的竞争条件。
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