公开(公告)号：US07489878B2

公开(公告)日：2009-02-10

申请号：US10834952

申请日：2004-04-28

申请人： Ashley Saulsbury

发明人： Ashley Saulsbury

IPC分类号： H04B10/04

CPC分类号： G06F21/556

摘要： A random noise generator is included in the drive circuit supplying power to a system indicator that emits optical signals. The random noise generator generates a random noise signal that is introduced into a signal input to the drive circuit so that data or covert channel information is not recoverable from the optical signals emitted by the system indicator.

摘要翻译： 驱动电路中包括随机噪声发生器，为发出光信号的系统指示器供电。 随机噪声发生器产生被引入到输入到驱动电路的信号的随机噪声信号，使得数据或隐蔽信道信息不能从系统指示器发射的光信号中恢复。

公开(公告)号：US07080234B2

公开(公告)日：2006-07-18

申请号：US09802120

申请日：2001-03-08

申请人： Ashley Saulsbury ,  Nyles Nettleton ,  Michael Parkin ,  David R. Emberson

发明人： Ashley Saulsbury ,  Nyles Nettleton ,  Michael Parkin ,  David R. Emberson

IPC分类号： G06F9/00

CPC分类号： G06F9/324 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3012 ,  G06F9/30181 ,  G06F9/321 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3889

摘要： According to the invention, a processing core (12) comprising a processing pipeline (100) having N-number of processing paths (56), each of which process instructions (54) on M-bit data words. In addition, the processing core (12) includes one or more register files (60), each preferably having Q-number of registers which are M-bits wide. Preferably, one of the Q-number of registers in at least one of the register files (60) is a program counter register dedicated to hold a program counter, and one of the Q-number of registers in at least one of the register files is a zero register dedicated to hold a zero value. In this manner, program jumps can be executed by adding values to the program counter in the program counter register, and memory address values can be calculated by adding values to the program counter stored in the program counter register or to the zero value stored in the zero register.

摘要翻译： 根据本发明，一种包括具有N个处理路径（56）的处理流水线（100）的处理核心（12），其中每个处理指令（54）在M位数据字上。 此外，处理核心（12）包括一个或多个寄存器文件（60），每个寄存器文件（60）优选地具有M位宽的寄存器的Q个数量。 优选地，至少一个寄存器文件（60）中的Q个寄存器之一是专用于保存程序计数器的程序计数器寄存器，并且至少一个寄存器堆栈中的一个寄存器中的一个 是一个专用于保持零值的零寄存器。 以这种方式，可以通过向程序计数器寄存器中的程序计数器添加值来执行程序跳转，并且可以通过将值附加到存储在程序计数器寄存器中的程序计数器或存储在程序计数器寄存器中的零值来计算存储器地址值 零寄存器

公开(公告)号：US07013321B2

公开(公告)日：2006-03-14

申请号：US09991628

申请日：2001-11-21

申请人： Ashley Saulsbury

发明人： Ashley Saulsbury

IPC分类号： G06F7/38

CPC分类号： G06F7/5443 ,  G06F2207/3828

摘要： According to the invention, a processing core that executes a parallel multiply accumulate operation is disclosed. Included in the processing core are a first, second and third input operand registers; a number of functional blocks; and, an output operand register. The first, second and third input operand registers respectively include a number of first input operands, a number of second input operands and a number of third input operands. Each of the number of functional blocks performs a multiply accumulate operation. The output operand register includes a number of output operands. Each of the number of output operands is related to one of the number of first input operands, one of the number of second input operands and one of the number of third input operands.

公开(公告)号：US20050035202A1

公开(公告)日：2005-02-17

申请号：US10834952

申请日：2004-04-28

申请人： Ashley Saulsbury

发明人： Ashley Saulsbury

IPC分类号： G06F21/00 ,  G06K7/10 ,  G06K7/14

CPC分类号： G06F21/556

摘要： A random noise generator is included in the drive circuit supplying power to a system indicator that emits optical signals. The random noise generator generates a random noise signal that is introduced into a signal input to the drive circuit so that data or covert channel information is not recoverable from the optical signals emitted by the system indicator.

摘要翻译： 驱动电路中包括随机噪声发生器，为发出光信号的系统指示器供电。 随机噪声发生器产生被引入到输入到驱动电路的信号的随机噪声信号，使得数据或隐蔽信道信息不能从系统指示器发射的光信号中恢复。

公开(公告)号：US06816961B2

公开(公告)日：2004-11-09

申请号：US09802121

申请日：2001-03-08

申请人： Daniel S. Rice ,  Ashley Saulsbury

发明人： Daniel S. Rice ,  Ashley Saulsbury

IPC分类号： G06F1700

CPC分类号： G06F9/30025 ,  G06F9/30032 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/3885

摘要： According to the invention, a processing core that includes a first source register, a second source register, a multiplexer, a destination register, and an operand processor is disclosed. The first source register includes a plurality of source fields. The second source register includes a number of result field select values and a number of operation fields. The multiplexer is coupled to at least one of the source fields. Included in the destination register is a plurality of result fields. The operand processor and multiplexer operate upon at least one of the source fields.

公开(公告)号：US08707332B2

公开(公告)日：2014-04-22

申请号：US13588191

申请日：2012-08-17

申请人： Ashley Saulsbury ,  Quinn A. Jacobson

发明人： Ashley Saulsbury ,  Quinn A. Jacobson

IPC分类号： G06F9/54

CPC分类号： G06F9/545 ,  G06F9/45558 ,  G06F9/546 ,  G06F2209/548

摘要： A computer-based method configures a hardware circuit to transfer a message to a message queue in an operating system. The hardware circuit is used to transfer a message to the message queue in the operating system without requiring use of either the operating system or a hypervisor associated with the operating system. The using the hardware circuit uses a logical identifier associated with the message to select an entry in a mapping table of the hardware circuit. A value in the entry in the mapping table is used to select an entry in an action table. The entry in the action table is used to determine a tail pointer for the message queue. The hardware circuit appends the message to a location indicted by the tail pointer without requiring cycles of a hypervisor associated with the strand.

摘要翻译： 基于计算机的方法配置硬件电路以将消息传送到操作系统中的消息队列。 硬件电路用于将消息传送到操作系统中的消息队列，而不需要使用操作系统或与操作系统相关联的管理程序。 使用硬件电路使用与消息相关联的逻辑标识符来选择硬件电路的映射表中的条目。 映射表中条目中的值用于在操作表中选择一个条目。 动作表中的条目用于确定消息队列的尾部指针。 硬件电路将消息附加到由尾部指针指示的位置，而不需要与该线束相关联的管理程序的周期。

公开(公告)号：US20120317588A1

公开(公告)日：2012-12-13

申请号：US13588191

申请日：2012-08-17

申请人： Ashley Saulsbury ,  Quinn A. Jacobson

发明人： Ashley Saulsbury ,  Quinn A. Jacobson

IPC分类号： G06F9/455

CPC分类号： G06F9/545 ,  G06F9/45558 ,  G06F9/546 ,  G06F2209/548

摘要： A computer-based method configures a hardware circuit to transfer a message to a message queue in an operating system. The hardware circuit is used to transfer a message to the message queue in the operating system without requiring use of either the operating system or a hypervisor associated with the operating system. The using the hardware circuit uses a logical identifier associated with the message to select an entry in a mapping table of the hardware circuit. A value in the entry in the mapping table is used to select an entry in an action table. The entry in the action table is used to determine a tail pointer for the message queue. The hardware circuit appends the message to a location indicted by the tail pointer without requiring cycles of a hypervisor associated with the strand.

摘要翻译： 基于计算机的方法配置硬件电路以将消息传送到操作系统中的消息队列。 硬件电路用于将消息传送到操作系统中的消息队列，而不需要使用操作系统或与操作系统相关联的管理程序。 使用硬件电路使用与消息相关联的逻辑标识符来选择硬件电路的映射表中的条目。 映射表中的条目中的值用于在操作表中选择一个条目。 动作表中的条目用于确定消息队列的尾部指针。 硬件电路将消息附加到由尾部指针指示的位置，而不需要与该线束相关联的管理程序的周期。

公开(公告)号：US20060161760A1

公开(公告)日：2006-07-20

申请号：US11026187

申请日：2004-12-30

申请人： Paul Jordan ,  William Kucharski ,  Roman Zajcew ,  Ashley Saulsbury ,  Quinn Jacobson

发明人： Paul Jordan ,  William Kucharski ,  Roman Zajcew ,  Ashley Saulsbury ,  Quinn Jacobson

IPC分类号： G06F9/44

CPC分类号： G06F12/1036 ,  G06F9/3851 ,  G06F12/1045 ,  G06F2212/1016

摘要： The present invention provides a method and apparatus for increased efficiency for translation lookaside buffers by collapsing redundant translation table entries into a single translation table entry (TTE). In the present invention, each thread of a multithreaded processor is provided with multiple context registers. Each of these context registers is compared independently to the context of the TTE. If any of the contexts match (and the other match conditions are satisfied), then the translation is allowed to proceed. Two applications attempting to share one page but that still keep separate pages can then employ three total contexts. One context is for one application's private use; one of the contexts is for the other application's private use; and a third context is for the shared page. In one embodiment of the invention, two contexts are implemented per thread. However, the teachings of the present invention can be extended to a higher number of contexts per thread.

摘要翻译： 本发明提供了一种用于通过将冗余转换表条目折叠到单个转换表条目（TTE）中来提高翻译后备缓冲器效率的方法和装置。 在本发明中，多线程处理器的每个线程都具有多个上下文寄存器。 这些上下文寄存器中的每一个独立地与TTE的上下文进行比较。 如果任何上下文匹配（并且满足其他匹配条件），则允许翻译继续。 尝试共享一个页面但仍然保持分页的两个应用程序可以使用三个总上下文。 一个上下文是一个应用程序的私人使用; 其中一个环境用于其他应用程序的私人使用; 第三个上下文是共享页面。 在本发明的一个实施例中，每个线程实现两个上下文。 然而，本发明的教导可以扩展到每个线程的更多数量的上下文。

公开(公告)号：US06892295B2

公开(公告)日：2005-05-10

申请号：US09802196

申请日：2001-03-08

申请人： Ashley Saulsbury

发明人： Ashley Saulsbury

IPC分类号： G06F9/30 ,  G06F9/345 ,  G06F9/355 ,  G06F9/38 ,  G06F7/02

CPC分类号： G06F9/30021 ,  G06F9/345 ,  G06F9/3842 ,  Y10T428/149

摘要： According to the invention, a method for processing data related to an array of elements is disclosed. In one embodiment, a method for processing data related to an array of elements is disclosed. In the process, a first value is loaded from a first location, and a second value is loaded from a second location. The first and second values are compared to each other. A predetermined value is optionally stored at a destination based upon the outcome of the comparison.

摘要翻译： 根据本发明，公开了一种用于处理与元件阵列有关的数据的方法。 在一个实施例中，公开了一种用于处理与元件阵列有关的数据的方法。 在该过程中，从第一位置加载第一值，并且从第二位置加载第二值。 将第一和第二值彼此进行比较。 基于比较的结果，可选地在目的地存储预定值。

公开(公告)号：US06631439B2

公开(公告)日：2003-10-07

申请号：US09802324

申请日：2001-03-08

申请人： Ashley Saulsbury ,  Nyles Nettleton ,  Michael Parkin

发明人： Ashley Saulsbury ,  Nyles Nettleton ,  Michael Parkin

IPC分类号： G06F1200

CPC分类号： G06F15/7857 ,  Y02D10/13

摘要： A novel processor chip (10) having a processing core (12), at least one bank of memory (14), an I/O link (26) configured to communicate with other like processor chips or compatible I/O devices, a memory controller (20) in electrical communication with processing core (12) and memory (14), and a distributed shared memory controller (22) in electrical communication with memory controller (20) and I/O link (26). Distributed shared memory controller (22) is configured to control the exchange of data between processor chip (10) and the other processor chips or I/O devices. In addition, memory controller (20) is configured to receive memory requests from processing core (12) and distributed shared memory controller (22) and process the memory request with memory (14). Processor chip (10) may further comprise an external memory interface (24) in electrical communication with memory controller (20). External memory interface (24) is configured to connect processor chip (10) with external memory, such as DRAM. Memory controller (20) is configured to receive memory requests from processing core (12) and distributed shared memory controller (22), determine whether the memory requests are directed to memory (14) on chip (10) or the external memory, and process the memory requests with memory (14) on processor chip (10) or with the external memory through external memory interface (24).