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1.发明授权VLIW computer processing architecture having the problem counter stored in a register file register 有权VLIW计算机处理架构将问题计数器存储在寄存器文件寄存器中公开(公告)号：US07080234B2
公开(公告)日：2006-07-18
申请号：US09802120
申请日：2001-03-08
IPC分类号： G06F9/00
CPC分类号： G06F9/324 , G06F9/30101 , G06F9/30105 , G06F9/3012 , G06F9/30181 , G06F9/321 , G06F9/3838 , G06F9/3851 , G06F9/3853 , G06F9/3889
摘要： According to the invention, a processing core (12) comprising a processing pipeline (100) having N-number of processing paths (56), each of which process instructions (54) on M-bit data words. In addition, the processing core (12) includes one or more register files (60), each preferably having Q-number of registers which are M-bits wide. Preferably, one of the Q-number of registers in at least one of the register files (60) is a program counter register dedicated to hold a program counter, and one of the Q-number of registers in at least one of the register files is a zero register dedicated to hold a zero value. In this manner, program jumps can be executed by adding values to the program counter in the program counter register, and memory address values can be calculated by adding values to the program counter stored in the program counter register or to the zero value stored in the zero register.
摘要翻译： 根据本发明，一种包括具有N个处理路径（56）的处理流水线（100）的处理核心（12），其中每个处理指令（54）在M位数据字上。 此外，处理核心（12）包括一个或多个寄存器文件（60），每个寄存器文件（60）优选地具有M位宽的寄存器的Q个数量。 优选地，至少一个寄存器文件（60）中的Q个寄存器之一是专用于保存程序计数器的程序计数器寄存器，并且至少一个寄存器堆栈中的一个寄存器中的一个 是一个专用于保持零值的零寄存器。 以这种方式，可以通过向程序计数器寄存器中的程序计数器添加值来执行程序跳转，并且可以通过将值附加到存储在程序计数器寄存器中的程序计数器或存储在程序计数器寄存器中的零值来计算存储器地址值 零寄存器
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公开(公告)号：US07043596B2
公开(公告)日：2006-05-09
申请号：US10113060
申请日：2002-03-29
申请人： Thomas M. McWilliams , Jeffrey B. Rubin , Michael W. Parkin , Oyekunle A. Olukotun , Derek E. Pappas , Jeffrey M. Broughton , David R. Emberson , David S. Allison , Ashley N. Saulsbury , Earl T. Cohen , Nyles I. Nettleton , James B. Burr , Liang T. Chen
发明人： Thomas M. McWilliams , Jeffrey B. Rubin , Michael W. Parkin , Oyekunle A. Olukotun , Derek E. Pappas , Jeffrey M. Broughton , David R. Emberson , David S. Allison , Ashley N. Saulsbury , Earl T. Cohen , Nyles I. Nettleton , James B. Burr , Liang T. Chen
CPC分类号： G06F17/5022 , G06F15/8023 , H04L49/10 , H04L49/101
摘要： A method and apparatus for computation is provided. A main cluster crossbar is connected to a plurality of statically scheduled routing processors. A first sub-cluster crossbar is associated with a first one of the plurality of statically scheduled routing processors where the first sub-cluster crossbar is connected to a first plurality of execution processors. A second sub-cluster crossbar is associated with a second one of the plurality of statically scheduled routing processors where the second sub-cluster crossbar is connected to a second plurality of execution processors.
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公开(公告)号：US07007268B2
公开(公告)日：2006-02-28
申请号：US10105977
申请日：2002-03-25
申请人： David R. Emberson
发明人： David R. Emberson
IPC分类号： G06F9/44
CPC分类号： G06F11/362
摘要： A method for performing debugging of an executable source program in a massively parallel processing environment involves associating a major cycle counter and a minor cycle counter with each of a plurality of execution processors in the massively parallel processing environment, obtaining a first stopping point value associated with the major cycle counter and a second stopping point value associated with the minor cycle counter, executing instructions of the executable source program on each of the plurality of execution processors, modifying the major cycle counter and the minor cycle counter, and halting each of the plurality of execution processors and returning control to the user if the major cycle counter reaches the first stopping point value and the minor cycle counter reaches the second stopping point value.
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公开(公告)号：US06205231B1
公开(公告)日：2001-03-20
申请号：US08435439
申请日：1995-05-10
IPC分类号： G06K900
CPC分类号： G06K9/38 , G01S3/7864 , G06K9/32 , G06T7/20 , H04N19/20
摘要： A moving object identification method (10) for identifying and tracing an object (20) within a video image (14) such that the object (20) can act as a hot spot (30) as for an interactive computer/user interface (70). A plurality of tags (28) define the edges (26) of the object (20) and a plurality of hot spot borders (32) define the hot spot (30) such that the hot spot (30) and the object (20) generally coincide. A physical tag (28b) is optionally used to position the tags (28). Sensitivity to disappearance of the edges (26) is adjustable according to the relative size of a subtag (68) to the corresponding tag (28).
摘要翻译： 一种用于识别和跟踪视频图像（14）内的对象（20）的运动对象识别方法（10），使得对象（20）可以作为交互式计算机/用户界面（70）的热点（30） ）。 多个标签（28）限定物体（20）的边缘（26），并且多个热点边界（32）限定热点（30），使得热点（30）和物体（20） 一般重合。 物理标签（28b）可选地用于定位标签（28）。 根据子标签（68）相对于相应标签（28）的相对大小，边缘（26）的消失灵敏度是可调节的。
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5.发明授权Method and apparatus for improving the fuel economy of a variable displacement engine 有权用于改善可变排量发动机的燃料经济性的方法和装置公开(公告)号：US08738270B2
公开(公告)日：2014-05-27
申请号：US13233599
申请日：2011-09-15
IPC分类号： G06F19/00
CPC分类号： F02D41/266 , F02D28/00 , F02D41/0087 , F02D2400/11
摘要： A secondary controller for controlling the performance of a moving automobile is described. The secondary controller can be configured to communicate with one or more vehicle controllers, such as the engine control unit, while the automobile is being driven. The secondary controller can send control commands, such as self-test or diagnostic commands to the vehicle controller to effect the operation of the vehicle's power train. The secondary controller can receive power train related data from the engine control unit and based upon the received power train data determine when to send the control commands. In one embodiment, the secondary controller communicates with the vehicle controller via the vehicle's diagnostic port, such as an OBD-II port. In another embodiment, the secondary controller can be configured to control a variable displacement engine in a vehicle to improve the fuel efficiency of the vehicle while it is driven.
摘要翻译： 描述了用于控制移动汽车的性能的二次控制器。 二次控制器可以被配置为在汽车被驱动时与一个或多个车辆控制器（例如发动机控制单元）通信。 二级控制器可以向车辆控制器发送诸如自检或诊断命令的控制命令，以实现车辆动力传动系的操作。 次级控制器可以从发动机控制单元接收动力传动系相关数据，并且基于所接收的动力传动系数据确定何时发送控制命令。 在一个实施例中，次级控制器经由车辆诊断端口（例如OBD-II端口）与车辆控制器通信。 在另一个实施例中，二级控制器可被配置成控制车辆中的可变排量发动机，以在车辆被驱动时提高车辆的燃料效率。
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6.发明授权Method for providing cycle-by-cycle ad HOC verification in a hardware-accelerated environment 有权在硬件加速环境中提供循环逐周期HOC验证的方法公开(公告)号：US07155378B2
公开(公告)日：2006-12-26
申请号：US10320108
申请日：2002-12-16
CPC分类号： G06F17/5022
摘要： A method of providing ad hoc verification for a simulation includes generating a cumulative record of a state value for the simulation of a circuit design, comparing the cumulative record of the state value to a golden record of the state value to obtain a comparison result, and performing ad hoc verification of the circuit design using the comparison result.
摘要翻译： 为仿真提供临时验证的方法包括生成用于模拟电路设计的状态值的累积记录，将状态值的累积记录与状态值的黄金记录进行比较以获得比较结果;以及 使用比较结果对电路设计进行临时验证。
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7.发明授权Method and apparatus for controlling a massively parallel processing environment 有权用于控制大规模并行处理环境的方法和装置公开(公告)号：US06957318B2
公开(公告)日：2005-10-18
申请号：US10112118
申请日：2002-03-28
CPC分类号： G06F17/5022
摘要： A method for controlling a processor array by a host computer involves creating a graph of a plurality of nodes using a data connection component, configuring a broadcast tree from a spanning tree of the graph, propagating a first command from the host computer to a member of the processor array using the broadcast tree, configuring a reply tree from a spanning tree of the graph, transmitting a response from the member of the processor array to the host computer using the reply tree, and configuring the data connection component to send at least one message selected from the first command and the response on at least one run mode communication path.
摘要翻译： 用于由主计算机控制处理器阵列的方法包括使用数据连接组件创建多个节点的图形，从图表的生成树配置广播树，将第一命令从主计算机传播到主机的成员 使用所述广播树的所述处理器阵列，从所述图的生成树配置回复树，使用所述答复树将所述处理器阵列的成员的响应发送到所述主计算机，以及配置所述数据连接组件以发送至少一个 从第一命令中选择的消息和至少一个运行模式通信路径上的响应。
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8.发明授权Tunable software control of harvard architecture cache memories using prefetch instructions 失效使用预取指令对哈佛架构高速缓存的可调软件进行控制
公开(公告)号：US5838945A
公开(公告)日：1998-11-17
申请号：US953220
申请日：1997-10-17
申请人： David R. Emberson
发明人： David R. Emberson
CPC分类号： G06F12/0862 , G06F9/383 , G06F12/0848 , G06F2212/6028
摘要： Disclosed is an instruction-level method and system for prefetching data or instructions of variable size to specified cache sets. A prefetch instruction containing binary fields allows the compiler, loader or runtime software to control cache prefetching and reduce thrashing by providing the prefetch hardware with information as to the optimal cache set location and the optimal amount of data to be prefetched. Support of Harvard architectures with separate instruction and data caches is provided by separate software control of instruction and data caches. The cache set number is identified to indicate into which set the information is to be preloaded. The size field provides a variable prefetch size. An address field indicates the address where prefetching begins.
摘要翻译： 公开了一种用于将数据或可变大小的指令预取到指定的缓存集的指令级方法和系统。 包含二进制字段的预取指令允许编译器，加载器或运行时软件通过向预取硬件提供关于最佳高速缓存集位置和要预取的最佳数据量的信息来控制高速缓存预取和减少抖动。 通过单独的指令和数据高速缓存的软件控制来提供具有单独指令和数据高速缓存的哈佛架构的支持。 识别高速缓存集编号以指示信息将被预加载到哪个集合中。 size字段提供可变预取大小。 地址字段表示预取开始的地址。
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9.发明授权Method and apparatus for accelerated post-silicon testing and random number generation 有权用于加速后硅测试和随机数生成的方法和装置公开(公告)号：US07133818B2
公开(公告)日：2006-11-07
申请号：US10417765
申请日：2003-04-17
IPC分类号： G06F17/50
CPC分类号： G01R31/318321 , G01R31/318342
摘要： A method of providing accelerated post-silicon testing for a silicon hardware includes computing a simulation cumulative record of state using a plurality of test instructions and a cycle breakpoint, performing a simulation of an instrumented logic design using the plurality of test instructions and the cycle breakpoint, manufacturing the silicon hardware using the instrumented logic design, computing a silicon cumulative record of state by executing the plurality of instructions using the silicon hardware; and comparing the simulation cumulative record of state to the silicon cumulative record of state.
摘要翻译： 为硅硬件提供加速后硅测试的方法包括使用多个测试指令和循环断点来计算状态的模拟累积记录，使用多个测试指令和循环断点执行仪表化逻辑设计的模拟 使用仪表逻辑设计制造硅硬件，通过使用硅硬件执行多条指令来计算硅累积状态记录; 并将状态的模拟累积记录与状态的硅累积记录进行比较。
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公开(公告)号：US07036114B2
公开(公告)日：2006-04-25
申请号：US10113005
申请日：2002-03-29
申请人： Thomas M. McWilliams , Jeffrey B. Rubin , Derek E. Pappas , Oyekunle A. Olukotun , Jeffrey M. Broughton , David R. Emberson , William kwei-cheung Lam , Liang T. Chen , Ihao Chen , Earl T. Cohen , Michael W. Parkin
发明人： Thomas M. McWilliams , Jeffrey B. Rubin , Derek E. Pappas , Oyekunle A. Olukotun , Jeffrey M. Broughton , David R. Emberson , William kwei-cheung Lam , Liang T. Chen , Ihao Chen , Earl T. Cohen , Michael W. Parkin
IPC分类号： G06F9/45
CPC分类号： G06F17/5022 , G06F2217/68
摘要： A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor array using static routing, a synchronization component enabling known timing relationships among the plurality of members of the processor array, a host service request component adapted to send a host service request from a member of the processor array to the host computer, and an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.
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