公开(公告)号：US5829033A

公开(公告)日：1998-10-27

申请号：US673059

申请日：1996-07-01

申请人： Erik Hagersten ,  Ashok Singhal ,  Bjorn Liencres

发明人： Erik Hagersten ,  Ashok Singhal ,  Bjorn Liencres

IPC分类号： G06F12/08 ,  G06F13/368 ,  G06F13/00

CPC分类号： G06F13/368 ,  G06F12/0831

摘要： In a computer system implementing state transitions that change logically and atomically at an address packet independently of a response, the coherence domain is extended among distributed memory. As such, memory line ownership transfers upon request, and not upon requestor receipt of data. Requestor receipt of data is rapidly implemented by providing a ReadToShareFork transaction that simultaneously causes a write-type operation that updates invalid data from a requested memory address, and provides the updated data to the requesting device. More specifically, when writing valid data to memory, the ReadToShare Fork transaction simultaneously causes reissuance of the originally requested transaction using the same memory address and ID information. The requesting device upon recognizing its transaction ID on the bus system will pull the now valid data from the desired memory location.

摘要翻译： 在实现状态转换的计算机系统中，其独立于响应在地址分组上逻辑地和原子地地改变，所述相干域在分布式存储器之间被扩展。 因此，内存线所有权根据请求转移，而不是请求者接收数据。 通过提供ReadToShareFork事务来快速实现数据的请求者接收，该事务同时导致从所请求的存储器地址更新无效数据的写入型操作，并将更新的数据提供给请求设备。 更具体地说，当向存储器写入有效数据时，ReadToShare Fork事务同时使用相同的存储器地址和ID信息来重新发出原始请求的事务。 请求设备在总线系统上识别其交易ID将从期望的存储器位置提​​取现在的有效数据。

公开(公告)号：US06578033B1

公开(公告)日：2003-06-10

申请号：US09597863

申请日：2000-06-20

申请人： Ashok Singhal ,  Erik Hagersten

发明人： Ashok Singhal ,  Erik Hagersten

IPC分类号： G06F1730

CPC分类号： G06F9/52 ,  Y10S707/99938

摘要： A probabilistic queue lock divides requesters for a lock into at least three sets. In one embodiment, the requesters are divided into the owner of the lock, the first waiting contender, and the other waiting contenders. The first waiting contender is made probabilistically more likely to obtain the lock by having it spin faster than the other waiting contenders. Because the other waiting contenders spin more slowly, the first waiting contender is more likely to be able to observe the free lock and acquire it before the other waiting contenders notice that it is free. The first of the other waiting contenders that determines that the previous first waiting contender has acquired the lock is promoted to be the new first waiting contender and begins spinning fast. Because only the first waiting contender is spinning fast on the lock, it is probable that only the first waiting contender will attempt to acquire the lock when it becomes available.

摘要翻译： 概率队列锁定将请求者锁定至少三组。 在一个实施例中，请求者被分为锁的所有者，第一等待竞争者和其他等待竞争者。 第一个等待竞争者的概率比其他等待竞争者更容易获得锁。 由于其他等待竞争者的旋转速度较慢，第一个等待竞争者更有可能在其他等待竞争者注意到自由之前观察到免费锁定并获得锁定。 第一个等待竞争者的第一个等待竞争者，确定先前的第一个等待竞争者已经获得锁被提升为新的第一个等待竞争者，并开始快速旋转。 因为只有第一个等待竞争者在锁上快速旋转，所以只有第一个等待竞争者才有可能尝试获取锁。

公开(公告)号：US5987549A

公开(公告)日：1999-11-16

申请号：US675286

申请日：1996-07-01

申请人： Erik Hagersten ,  Ashok Singhal

发明人： Erik Hagersten ,  Ashok Singhal

IPC分类号： G06F12/08 ,  G06F13/368 ,  G06F13/00

CPC分类号： G06F12/0831 ,  G06F13/368

摘要： Low-latency distributed round-robin arbitration is used to grant requests for access to a shared resource such as a computer system bus. A plurality of circuit board cards that each include two devices such as CPUs, I/O units, and ram and an address controller plugs into an Address Bus in the bus system. Each address controller contains logic implementing the arbitration mechanism with a two-level hierarchy: a single top arbitrator and preferably four leaf arbitrators. Each address controller is coupled to two devices and the logical "OR" of their arbitration request is coupled via an Arbitration Bus to other address controllers on other boards. Each leaf arbitrator has four prioritized request in lines, each such line being coupled to a single address controller serviced by that leaf arbitrator. By default, each leaf arbitrator and the top arbitrator implement a prioritized algorithm. However a last winner ("LW") state is maintained at every arbitrator that overrides the default, to provide round-robin selection. Each leaf arbitrator arbitrates among the zero to four requests it sees, selects a winner and signals the top arbitrator that it has a device wishing access. At the top arbitrator, if the first leaf arbitrator last won a grant, it now has lowest grant priority, and a grant will go to the next highest leaf arbitrator having a device seeking access.

摘要翻译： 低延迟分布式循环仲裁用于授予访问共享资源（如计算机系统总线）的请求。 多个电路板卡每个包括诸如CPU，I / O单元和RAM的两个设备和地址控制器插入总线系统中的地址总线中。 每个地址控制器包含实现具有两级层次的仲裁机制的逻辑：单个顶级仲裁器，最好是四个叶子仲裁器。 每个地址控制器耦合到两个设备，并且其仲裁请求的逻辑“或”通过仲裁总线耦合到其他板上的其他地址控制器。 每个叶子仲裁器具有四个优先级的请求，每个这样的行被耦合到该叶子仲裁器所服务的单个地址控制器。 默认情况下，每个叶子仲裁器和顶级仲裁器实现优先级算法。 然而，每个仲裁员维护最后一个赢家（“LW”）状态，以覆盖默认值，以提供循环选择。 每个叶仲裁员在它看到的零到四个请求之间进行仲裁，选择一个获胜者，并向顶级仲裁员发出信号，指示它具有希望访问的设备。 在最高的仲裁员身上，如果第一个叶子仲裁员最后一次获得授权，那么它现在具有最低的授权优先权，而授权将转到具有寻求访问权限的设备的下一个最高的叶子仲裁员。

公开(公告)号：US20050044174A1

公开(公告)日：2005-02-24

申请号：US10821729

申请日：2004-04-09

申请人： Anders Landin ,  Robert Cypher ,  Erik Hagersten ,  Ashok Singhal

发明人： Anders Landin ,  Robert Cypher ,  Erik Hagersten ,  Ashok Singhal

IPC分类号： G06F12/08 ,  G06F15/16

CPC分类号： G06F12/0817 ,  G06F12/0813 ,  G06F12/0831

摘要： A system may include a plurality of nodes coupled by an inter-node network. Each of the nodes includes several active devices, an interface to the inter-node network, and an address network coupling the active devices to the interface. An active device included in one of the nodes initiates a transaction by sending either a first type of address packet or a second type of address packet on the address network dependent on whether the active device is included in a multi-node system. The first type of address packet is sent if the active device is included in a multi-node system and is not snooped by other active devices in the same node as the active device. The second type of address packet, sent if the active device is included in a single node system, is snooped by other active devices in the same node as the active device.

摘要翻译： 系统可以包括由节点间网络耦合的多个节点。 每个节点包括若干活动设备，节点间网络的接口以及将活动设备耦合到接口的地址网络。 包括在其中一个节点中的活动设备通过在地址网络上发送第一类型的地址分组或第二类型的地址分组来发起交易，这取决于活动设备是否包括在多节点系统中。 如果活动设备包括在多节点系统中并且不与主动设备在同一节点中的其他活动设备进行窥探，则发送第一类地址分组。 如果活动设备包含在单个节点系统中，则发送的第二种类型的地址分组被与活动设备在同一节点中的其他活动设备进行探测。

公开(公告)号：US6148300A

公开(公告)日：2000-11-14

申请号：US100667

申请日：1998-06-19

申请人： Ashok Singhal ,  Erik Hagersten

发明人： Ashok Singhal ,  Erik Hagersten

IPC分类号： G06F9/52 ,  G06F9/46 ,  G06F13/00 ,  G06F17/30

CPC分类号： G06F9/52 ,  Y10S707/99938

摘要： A probabilistic queue lock divides requesters for a lock into at least three sets. In one embodiment, the requesters are divided into the owner of the lock, the first waiting contender, and the other waiting contenders. The first waiting contender is made probabilistically more likely to obtain the lock by having it spin faster than the other waiting contenders. Because the other waiting contenders spin more slowly, the first waiting contender is more likely to be able to observe the free lock and acquire it before the other waiting contenders notice that it is free. The first of the other waiting contenders that determines that the previous first waiting contender has acquired the lock is promoted to be the new first waiting contender and begins spinning fast. Because only the first waiting contender is spinning fast on the lock, it is probable that only the first waiting contender will attempt to acquire the lock when it becomes available.

摘要翻译： 概率队列锁定将请求者锁定至少三组。 在一个实施例中，请求者被分为锁的所有者，第一等待竞争者和其他等待竞争者。 第一个等待竞争者的概率比其他等待竞争者更容易获得锁。 因为其他等待竞争者的转动速度更慢，所以第一个等待竞争者更有可能在其他等待竞争者注意到它是免费的前提下观察到自由锁。 第一个等待竞争者的第一个等待竞争者，确定先前的第一个等待竞争者已经获得锁被提升为新的第一个等待竞争者，并开始快速旋转。 因为只有第一个等待竞争者在锁上快速旋转，所以只有第一个等待竞争者才有可能尝试获取锁。

公开(公告)号：US5978874A

公开(公告)日：1999-11-02

申请号：US673038

申请日：1996-07-01

申请人： Ashok Singhal ,  Bjorn Liencres ,  Jeff Price ,  Frederick M. Cerauskis ,  David Broniarczyk ,  Gerald Cheung ,  Erik Hagersten ,  Nalini Agarwal

发明人： Ashok Singhal ,  Bjorn Liencres ,  Jeff Price ,  Frederick M. Cerauskis ,  David Broniarczyk ,  Gerald Cheung ,  Erik Hagersten ,  Nalini Agarwal

IPC分类号： G06F12/08 ,  G06F13/368 ,  G06F13/00

CPC分类号： G06F13/368 ,  G06F12/0831

摘要： Snooping is implemented on a split transaction snooping bus for a computer system having one or many such buses. Circuit boards including CPU or other devices and/or distributed memory, data input/output buffers, queues including request tag queues, coherent input queues ("CIQ"), and address controller implementing address bus arbitration plug-into one or more split transaction snooping bus systems. All devices snoop on the address bus to learn whether an identified line is owned or shared, and an appropriate owned/shared signal is issued. Receipt of an ignore signal blocks CIQ loading of a transaction until the transaction is reloaded and ignore is deasserted. Ownership of a requested memory line transfers immediately at time of request. Asserted requests are queued such that state transactions on the address bus occur atomically logically without dependence upon the request. Subsequent requests for the same data are tagged to become the responsibility of the owner-requestor. A subsequent requestor's activities are not halted awaiting grant and completion of an earlier request transaction. Processor-level cache changes state upon receipt of transaction data. A single multiplexed arbitration bus carries address bus and data bus request transactions, which transactions are each two-cycles in length.

摘要翻译： 在具有一个或多个这样的总线的计算机系统的分离事务监听总线上实现侦听。 电路板包括CPU或其他设备和/或分布式存储器，数据输入/输出缓冲器，包括请求标签队列，相干输入队列（“CIQ”）和地址控制器的队列，实现地址总线仲裁插入到一个或多个拆分事务监听 总线系统 所有设备在地址总线上窥探，了解所标识的行是否拥有或共享，并发出适当的拥有/共享信号。 接收忽略信号阻止事务的CIQ加载，直到重新加载事务并忽略忽略。 所请求的内存线的所有权在请求时立即转移。 被排除的请求排队，使得地址总线上的状态事务在逻辑上发生，而不依赖于请求。 对相同数据的后续请求被标记为成为所有者请求者的责任。 后续请求者的活动不会暂停等待授予并完成较早的请求事务。 处理器级缓存在收到交易数据后更改状态。 单个复用仲裁总线承载地址总线和数据总线请求事务，这些事务的长度分别为两个周期。

公开(公告)号：US5911052A

公开(公告)日：1999-06-08

申请号：US673967

申请日：1996-07-01

申请人： Ashok Singhal ,  Bjorn Liencres ,  Jeff Price ,  Frederick M. Cerauskis ,  David Broniarczyk ,  Gerald Cheung ,  Erik Hagersten ,  Nalini Agarwal

发明人： Ashok Singhal ,  Bjorn Liencres ,  Jeff Price ,  Frederick M. Cerauskis ,  David Broniarczyk ,  Gerald Cheung ,  Erik Hagersten ,  Nalini Agarwal

IPC分类号： G06F12/08 ,  G06F13/368 ,  G06F13/00

CPC分类号： G06F13/368 ,  G06F12/0831

摘要： A split transaction snooping bus protocol and architecture is provided for use in a system having one or many such buses. Circuit boards including CPU or other devices and/or distributed memory, data input/output buffers, queues including request tag queues, coherent input queues ("CIQ"), and address controller implementing address bus arbitration plug-into one or more split transaction snooping bus systems. All devices snoop on the address bus to learn whether an identified line is owned or shared, and an appropriate owned/shared signal is issued. Receipt of an ignore signal blocks CIQ loading of a transaction until the transaction is reloaded and ignore is deasserted. Ownership of a requested memory line transfers immediately at time of request. Asserted requests are queued such that state transactions on the address bus occur atomically logically without dependence upon the request. Subsequent requests for the same data are tagged to become the responsibility of the owner-requestor. A subsequent requestor's activities are not halted awaiting grant and completion of an earlier request transaction. Processor-level cache changes state upon receipt of transaction data. A single multiplexed arbitration bus carries address bus and data bus request transactions, which transactions are each two-cycles in length.

摘要翻译： 分组交易监听总线协议和架构被提供用于具有一个或多个这样的总线的系统中。 电路板包括CPU或其他设备和/或分布式存储器，数据输入/输出缓冲器，包括请求标签队列，相干输入队列（“CIQ”）和地址控制器的队列，实现地址总线仲裁插入到一个或多个拆分事务监听 总线系统 所有设备在地址总线上窥探，了解所标识的行是否拥有或共享，并发出适当的拥有/共享信号。 接收忽略信号阻止事务的CIQ加载，直到重新加载事务并忽略忽略。 所请求的内存线的所有权在请求时立即转移。 被排除的请求排队，使得地址总线上的状态事务在逻辑上发生，而不依赖于请求。 对相同数据的后续请求被标记为成为所有者请求者的责任。 后续请求者的活动不会暂停等待授予并完成较早的请求事务。 处理器级缓存在收到交易数据后更改状态。 单个复用仲裁总线承载地址总线和数据总线请求事务，这些事务的长度分别为两个周期。

公开(公告)号：US5778427A

公开(公告)日：1998-07-07

申请号：US499590

申请日：1995-07-07

申请人： Erik Hagersten ,  Ashok Singhal

发明人： Erik Hagersten ,  Ashok Singhal

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/1054 ,  G06F12/0864 ,  G06F2212/6082

摘要： The present invention provides a cache manager (CM) for use with an address translation table (ATT) which take advantage of way information, available when a cache line is first cached, for efficiently accessing a multi-way cache of a computer system having a main memory and one or more processors. The main memory and the ATT are page-oriented while the cache is organized using cache lines. The cache includes a plurality of cache lines divided into a number of segments corresponding to the number of "ways". Each cache line includes an address tag (AT) field and a data field. The way information is stored in the ATT for later cache access. In this implementation, "waylets" provide an efficiency mechanism for storing the way information whenever a cache line is cached. Accordingly, each table entry of the ATT includes a virtual address (VA) field, a physical address (PA) field, and a plurality of waylets associated with each pair of VA and PA fields. Subsequently, the waylets can be used to quickly index directly into a single segment of the cache as follows. Upon receiving a virtual address of a target cache line, the CM attempts to match a virtual address field of one of the ATT entries with a page index portion of the virtual address. If there is a match, a waylet of the ATT entry is retrieved using a page offset portion of the virtual address. If the waylet value is valid, the CM indexes directly into a single cache line using the waylet value, the physical address field of the ATT entry and the page offset portion of the virtual address. If the AT field of the retrieved cache line matches with a portion of the physical address field of the ATT entry, the processor retrieves the data field of the cache line using the page offset portion of the VA. If the AT field does not match, the target cache line is retrieved from the main memory, and the waylet value in both the ATT and the main memory is updated.

公开(公告)号：US07222220B2

公开(公告)日：2007-05-22

申请号：US10601402

申请日：2003-06-23

申请人： Robert E. Cypher ,  Ashok Singhal

发明人： Robert E. Cypher ,  Ashok Singhal

IPC分类号： G06F12/12

CPC分类号： G06F12/0815 ,  G06F12/0817 ,  G06F12/0831

摘要： A multiprocessor computer system is configured to selectively transmit address transactions through an address network using either a broadcast mode or a point-to-point mode transparent to the active devices that initiate the transactions. Depending on the mode of transmission selected, either a directory-based coherency protocol or a broadcast snooping coherency protocol is implemented to maintain coherency within the system. A computing node is formed by a group of clients which share a common address and data network. The address network is configured to determine whether a particular transaction is to be conveyed in broadcast mode or point-to-point mode. In one embodiment, the address network includes a mode table with entries which are configurable to indicate transmission modes corresponding to different regions of the address space within the node. Upon receiving a coherence request transaction, the address network may then access the table in order to determine the transmission mode, broadcast or point-to-point, which corresponds to the received transaction.

摘要翻译： 多处理器计算机系统被配置为通过地址网络选择性地发送地址事务，所述地址网络使用对启动事务的活动设备透明的广播模式或点对点模式。 根据所选择的传输模式，实现基于目录的一致性协议或广播窥探一致性协议，以保持系统内的一致性。 计算节点由共享公共地址和数据网络的一组客户端形成。 地址网络被配置为确定特定事务是以广播模式还是点对点模式传送。 在一个实施例中，地址网络包括具有可配置为指示对应于节点内的地址空间的不同区域的传输模式的条目的模式表。 在接收到一致性请求事务时，地址网络然后可以访问该表，以便确定对应于所接收的事务的传输模式，广播或点对点。

公开(公告)号：US20060259687A1

公开(公告)日：2006-11-16

申请号：US11269024

申请日：2005-11-07

申请人： Sushil Thomas ,  Ashok Singhal

发明人： Sushil Thomas ,  Ashok Singhal

IPC分类号： G06F12/16 ,  G06F12/00

CPC分类号： G06F3/0647 ,  G06F3/0607 ,  G06F3/0689

摘要： A method is provided for a data storage system to change the RAID type, the layout characteristics, and the performance characteristics of a virtual volume mapped to logical disk regions in one or more logical disks while the data storage system remains online to a host. Another method is provided for a data storage system to consolidate space in one or more logical disks mapped to a virtual volume while the data storage system remains online to a host. The one or more logical disks can be consolidated to free unused chunklet regions for use in other logical disks.

摘要翻译： 为数据存储系统提供了一种方法，用于在数据存储系统保持联机到主机时，改变映射到一个或多个逻辑磁盘中的逻辑磁盘区域的虚拟卷的RAID类型，布局特性和性能特征。 为数据存储系统提供另一种方法，以便在数据存储系统保持与主机联机的情况下，整合映射到虚拟卷的一个或多个逻辑磁盘中的空间。 可以合并一个或多个逻辑磁盘以释放用于其他逻辑磁盘的未使用的chunklet区域。