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公开(公告)号：US09362894B1
公开(公告)日：2016-06-07
申请号：US14702776
申请日：2015-05-04
CPC分类号： H03K5/1565 , H03K5/19 , H03K5/24
摘要： A clock generator includes a diagnostic circuit that includes first and second muxes, first and second comparators, a logic gate, and a counter. The first mux receives first and second voltage signals and outputs a first intermediate signal based on a control signal. The second mux receives third and fourth voltage signals and outputs a second intermediate signal based on the control signal. The first and second comparators compare the intermediate signals with a first signal that is indicative of a DC value of the clock signal for generating first and second comparison signals. The logic gate receives the first and second intermediate signals and generates a control signal. The counter receives the clock signal and the control signal and generates a clock ready signal that is indicative of stability and quality of the clock signal.
摘要翻译： 时钟发生器包括包括第一和第二多路复用器的诊断电路，第一和第二比较器，逻辑门和计数器。 第一复用器接收第一和第二电压信号，并且基于控制信号输出第一中间信号。 第二复用器接收第三和第四电压信号，并且基于控制信号输出第二中间信号。 第一和第二比较器将中间信号与表示用于产生第一和第二比较信号的时钟信号的DC值的第一信号进行比较。 逻辑门接收第一和第二中间信号并产生控制信号。 计数器接收时钟信号和控制信号，并产生指示时钟信号的稳定性和质量的时钟就绪信号。
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公开(公告)号：US09252791B1
公开(公告)日：2016-02-02
申请号：US14580136
申请日：2014-12-22
CPC分类号： H03L7/099 , H03L7/104 , H03L2207/06
摘要： A phase locked loop (PLL) system generates an oscillator signal by providing a fixed control voltage to a programmable voltage to current converter having switch selection inputs and a variable current output. Logic values are provided to the switch selection inputs to adjust a control current at the variable current output and a frequency of the oscillator signal is adjusted based on the control current. The logic values are fixed when a first condition is reached, which is based on the frequency of the oscillator signal, a division factor, and an input reference signal frequency. The fixed control voltage provided to the programmable voltage to current converter is then replaced with a charge pump control voltage based on an error signal. The error signal is based on a comparison of the input reference signal frequency and a fraction of the oscillating frequency.
摘要翻译： 锁相环（PLL）系统通过向具有开关选择输入和可变电流输出的可编程电压到电流转换器提供固定的控制电压来产生振荡器信号。 将逻辑值提供给开关选择输入，以调整可变电流输出端的控制电流，并根据控制电流调整振荡器信号的频率。 当达到基于振荡器信号的频率，分频因子和输入参考信号频率的第一条件时，逻辑值是固定的。 然后，提供给可编程电压到电流转换器的固定控制电压由基于误差信号的电荷泵控制电压代替。 误差信号基于输入参考信号频率和振荡频率的一小部分的比较。
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公开(公告)号：US09209747B1
公开(公告)日：2015-12-08
申请号：US14614427
申请日：2015-02-05
申请人： Anand Kumar Sinha , Ashish Ojha , Ateet Omer
发明人： Anand Kumar Sinha , Ashish Ojha , Ateet Omer
IPC分类号： H03B5/36
CPC分类号： H03B5/364 , H03B5/06 , H03B2200/0066
摘要： An oscillator includes an amplifier and a piezoelectric crystal coupled across a portion of the amplifier. A low pass filter (LPF) passes the common-mode voltage component of the crystal output signal. An auxiliary bias circuit uses a shared LPF component to charge a crystal load capacitor during start-up of the oscillator, and to provide a DC bias operating point to the oscillator driver transistor. A buffer amplifier receives the common-mode voltage component on the non-inverting input. The buffer amplifier output is coupled to both the inverting input and the drain terminal of the oscillator driver transistor such that the gate and drain DC bias voltages of the oscillator driver transistor are substantially the same. An automatic loop control circuit receives the crystal output signal and the common-mode voltage signal, and generates a bias control signal to bias the amplifier and the auxiliary bias circuit.
摘要翻译： 振荡器包括放大器和耦合在放大器的一部分上的压电晶体。 低通滤波器（LPF）通过晶体输出信号的共模电压分量。 辅助偏置电路在振荡器启动期间使用共享LPF分量对晶体负载电容器充电，并向振荡器驱动晶体管提供DC偏置工作点。 缓冲放大器在非反相输入端接收共模电压分量。 缓冲放大器输出耦合到振荡器驱动晶体管的反相输入和漏极端，使得振荡器驱动晶体管的栅极和漏极直流偏置电压基本上相同。 自动回路控制电路接收晶体输出信号和共模电压信号，并产生偏置控制信号以偏置放大器和辅助偏置电路。
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4.发明申请CAPACITOR CHARGING CIRCUIT WITH LOW SUB-THRESHOLD TRANSISTOR LEAKAGE CURRENT 有权具有低子阈值晶体管漏电流的电容器充电电路公开(公告)号：US20140197806A1
公开(公告)日：2014-07-17
申请号：US13743323
申请日：2013-01-16
IPC分类号： H02J7/00
CPC分类号： H03K4/06
摘要： A capacitor charging circuit has input, output and control nodes, first and second series connected primary FETs, and first and second leakage current reduction FETs. All of the FETs have their gates coupled to the control node. The first primary FET is coupled between the input and output nodes, and the second primary FET is coupled between the output node and a leakage current reduction node. The first leakage current reduction FET is coupled between a supply line and the leakage current reduction node, and the second leakage current reduction FET is coupled between the leakage current reduction node and ground. When a control signal at the control node is low, the first primary FET and the first leakage current reduction FET are conductive, and the second primary FET and the second leakage current reduction FET are non-conductive, which eliminates sub-threshold leakage current flowing through the second primary FET.
摘要翻译： 电容充电电路具有输入，输出和控制节点，第一和第二串联连接的主要FET以及第一和第二漏电流减少FET。 所有的FET都具有耦合到控制节点的门。 第一主FET耦合在输入和输出节点之间，第二主要FET耦合在输出节点和漏电流减少节点之间。 第一泄漏电流降低FET耦合在电源线和漏电流减小节点之间，并且第二漏电流减小FET耦合在漏电流减少节点和地之间。 当控制节点处的控制信号为低电平时，第一初级FET和第一漏电流降低FET导通，并且第二初级FET和第二漏电流减小FET不导通，这消除了亚阈值漏电流流动 通过第二个主要FET。
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公开(公告)号：US20140210564A1
公开(公告)日：2014-07-31
申请号：US13753544
申请日：2013-01-30
IPC分类号： H03K3/36
CPC分类号： H03K3/0231
摘要： A relaxation oscillator for generating an output clock signal includes an RC circuit, a self-biased comparator stage, and a logic circuit. The RC circuit generates first and second comparator input signals that are provided to the self-biased comparator stage. The self-biased comparator stage includes first and second input stages and a voltage reference circuit. Each of the first and second input stages in conjunction with the voltage reference circuit forms a comparator, i.e., first and second comparators corresponding to the first and second input stages, respectively. The self-biased comparator stage generates first and second comparator output signals, based on the first and second comparator input signals. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal.
摘要翻译： 用于产生输出时钟信号的放大振荡器包括RC电路，自偏置比较器级和逻辑电路。 RC电路产生提供给自偏置比较器级的第一和第二比较器输入信号。 自偏置比较器级包括第一和第二输入级和电压参考电路。 第一和第二输入级中的每一个结合电压参考电路分别形成比较器，即分别对应于第一和第二输入级的第一和第二比较器。 自偏置比较器级基于第一和第二比较器输入信号产生第一和第二比较器输出信号。 第一和第二比较器输出信号被提供给产生输出时钟信号的逻辑电路。
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公开(公告)号：US08803619B1
公开(公告)日：2014-08-12
申请号：US13753544
申请日：2013-01-30
CPC分类号： H03K3/0231
摘要： A relaxation oscillator for generating an output clock signal includes an RC circuit, a self-biased comparator stage, and a logic circuit. The RC circuit generates first and second comparator input signals that are provided to the self-biased comparator stage. The self-biased comparator stage includes first and second input stages and a voltage reference circuit. Each of the first and second input stages in conjunction with the voltage reference circuit forms a comparator, i.e., first and second comparators corresponding to the first and second input stages, respectively. The self-biased comparator stage generates first and second comparator output signals, based on the first and second comparator input signals. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal.
摘要翻译： 用于产生输出时钟信号的放大振荡器包括RC电路，自偏置比较器级和逻辑电路。 RC电路产生提供给自偏置比较器级的第一和第二比较器输入信号。 自偏置比较器级包括第一和第二输入级和电压参考电路。 第一和第二输入级中的每一个结合电压参考电路分别形成比较器，即分别对应于第一和第二输入级的第一和第二比较器。 自偏置比较器级基于第一和第二比较器输入信号产生第一和第二比较器输出信号。 第一和第二比较器输出信号被提供给产生输出时钟信号的逻辑电路。
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7.发明授权公开(公告)号：US09065433B2
公开(公告)日：2015-06-23
申请号：US13743323
申请日：2013-01-16
CPC分类号： H03K4/06
摘要： A capacitor charging circuit has input, output and control nodes, first and second series connected primary FETs, and first and second leakage current reduction FETs. All of the FETs have their gates coupled to the control node. The first primary FET is coupled between the input and output nodes, and the second primary FET is coupled between the output node and a leakage current reduction node. The first leakage current reduction FET is coupled between a supply line and the leakage current reduction node, and the second leakage current reduction FET is coupled between the leakage current reduction node and ground. When a control signal at the control node is low, the first primary FET and the first leakage current reduction FET are conductive, and the second primary FET and the second leakage current reduction FET are non-conductive, which eliminates sub-threshold leakage current flowing through the second primary FET.
摘要翻译： 电容充电电路具有输入，输出和控制节点，第一和第二串联连接的主要FET以及第一和第二漏电流减少FET。 所有的FET都具有耦合到控制节点的门。 第一主FET耦合在输入和输出节点之间，第二主要FET耦合在输出节点和漏电流减少节点之间。 第一泄漏电流降低FET耦合在电源线和漏电流减小节点之间，并且第二漏电流减小FET耦合在漏电流减少节点和地之间。 当控制节点处的控制信号为低电平时，第一初级FET和第一漏电流降低FET导通，并且第二初级FET和第二漏电流减小FET不导通，这消除了亚阈值漏电流流动 通过第二个主要FET。
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公开(公告)号：US08390347B1
公开(公告)日：2013-03-05
申请号：US13402844
申请日：2012-02-22
IPC分类号： H03L7/06
CPC分类号： H03L7/1077 , H03L7/085 , H03L7/089
摘要： A phase to digital converter for a digital PLL (Phase Locked Loop) provides an output in the same or single reference clock period for which it is digitizing the phase error information. The phase to digital converter operates on a positive edge of the reference clock and a digital filter operates on the negative edge of the reference clock so the phase correction performed by the PLL occurs in the same reference clock cycle in which the phase to digital converter is digitizing the phase error information.
摘要翻译： 用于数字PLL（锁相环）的相位数字转换器提供在相位或单个参考时钟周期内的输出，为此数字转换器正在数字化相位误差信息。 相位到数字转换器在参考时钟的上升沿工作，数字滤波器在参考时钟的负沿工作，因此PLL执行的相位校正发生在相位到数字转换器的相同参考时钟周期 数字化相位误差信息。
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