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    Peripheral interface circuit for serial memory
    1.
    发明授权
    Peripheral interface circuit for serial memory 有权

    公开(公告)号：US10725950B2

    公开(公告)日：2020-07-28

    申请号：US16140486

    申请日：2018-09-24

    Applicant: Atmel Corporation

    Inventor： Frédéric Schumacher ,  Guillaume Pean ,  Renaud Tiennot

    IPC: G06F13/362 ,  G06F13/16 ,  G06F13/42

    Abstract: A peripheral interface circuit and method is disclosed for dealing with round trip delay with serial memory. In some implementations, a finite state machine is configured to introduce a delay state prior to a read data state to absorb round trip delay associated with a memory read operation. A clock module is coupled to the finite state machine and configured to delay start of a pad return clock for the read operation until completion of the delay state. A first synchronous logic is coupled to receive the pad return clock and is configured to sample and hold data from a data bus during the read data state of the memory read operation based on the pad return clock. A second synchronous logic is coupled to receive a system clock and is configured to sample the held data based on the system clock.

    Proactive quality of service in multi-matrix system bus
    2.
    发明授权
    Proactive quality of service in multi-matrix system bus 有权
    多矩阵系统总线的主动服务质量

    公开(公告)号：US09372818B2

    公开(公告)日：2016-06-21

    申请号：US13840681

    申请日：2013-03-15

    Applicant: ATMEL CORPORATION

    Inventor： Franck Lunadier ,  Eric Matulik ,  Renaud Tiennot

    IPC: G06F13/00 ,  G06F13/368 ,  G06F12/00 ,  G06F13/14 ,  G06F13/38

    CPC classification number: G06F13/362 ,  G06F13/368 ,  G06F13/4022 ,  G06F13/4068

    Abstract: A multi-matrix bus system is disclosed that provides proactive quality of service (QoS) by propagating, as soon as possible through an arbitration node in a network transfer request path, a highest priority value coming from an upstream arbitration node or master that has a current bus request pending at the arbitration node. The bus system ensures that any last downstream arbitration node knows at any time which is the highest priority request pending in the network transfer request path from the masters that are competing to share the bus layer switches and arbitration nodes in the network transfer request path.

    Abstract translation: 公开了一种多矩阵总线系统，其通过在网络传送请求路径中通过仲裁节点尽可能快地传播来自上游仲裁节点或主机的最高优先级值来提供主动服务质量（QoS） 当前总线请求在仲裁节点挂起。 总线系统确保任何最后一个下行仲裁节点在任何时候都知道网络传输请求路径中等待的最高优先级请求是来自正在竞争共享总线层交换机和仲裁节点的网络传输请求路径中的主机。

    Microcontroller with integrated interface enabling reading data randomly from serial flash memory
    3.
    发明授权
    Microcontroller with integrated interface enabling reading data randomly from serial flash memory 有权
    具有集成接口的微控制器，可从串行闪存随机读取数据

    公开(公告)号：US09329782B2

    公开(公告)日：2016-05-03

    申请号：US14505610

    申请日：2014-10-03

    Applicant: Atmel Corporation

    Inventor： Frédéric Schumacher ,  Guillaume Pean ,  Renaud Tiennot

    IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F13/00

    CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/00 ,  G06F13/1694 ,  G06F2206/1014

    Abstract: A microcontroller includes a microprocessor, a serial flash memory interface, and input/output (I/O) terminals for coupling the serial flash memory interface to external serial flash memory. The microprocessor is operable to generate instruction frames that trigger respective commands to read data from specified addresses in the external serial flash memory. The serial flash memory interface receives and processes the instruction frames, obtains the data contained in the specified addresses in the external serial flash memory regardless of whether the specified addresses are sequential or non-sequential, and provides the data for use by the microprocessor.

    Abstract translation: 微控制器包括微处理器，串行闪存接口和用于将串行闪存接口耦合到外部串行闪存的输入/输出（I / O）端子。 微处理器可操作以产生触发相应命令以从外部串行闪存中的指定地址读取数据的指令帧。 串行闪存接口接收并处理指令帧，获取外部串行闪存中指定地址中包含的数据，而不管指定的地址是顺序还是非顺序，并提供数据供微处理器使用。

    MICROCONTROLLER WITH INTEGRATED INTERFACE ENABLING READING DATA RANDOMLY FROM SERIAL FLASH MEMORY
    4.
    发明申请
    MICROCONTROLLER WITH INTEGRATED INTERFACE ENABLING READING DATA RANDOMLY FROM SERIAL FLASH MEMORY 有权
    具有集成接口的微控制器从串行闪存中随机读取数据

    公开(公告)号：US20140095764A1

    公开(公告)日：2014-04-03

    申请号：US13630002

    申请日：2012-09-28

    Applicant: ATMEL CORPORATION

    Inventor： Frédéric Schumacher ,  Guillaume Pean ,  Renaud Tiennot

    IPC: G06F12/00

    CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/00 ,  G06F13/1694 ,  G06F2206/1014

    Abstract: A microcontroller includes a microprocessor, a serial flash memory interface, and input/output (I/O) terminals for coupling the serial flash memory interface to external serial flash memory. The microprocessor is operable to generate instruction frames that trigger respective commands to read data from specified addresses in the external serial flash memory. The serial flash memory interface receives and processes the instruction frames, obtains the data contained in the specified addresses in the external serial flash memory regardless of whether the specified addresses are sequential or non-sequential, and provides the data for use by the microprocessor.

    Abstract translation: 微控制器包括微处理器，串行闪存接口和用于将串行闪存接口耦合到外部串行闪存的输入/输出（I / O）端子。 微处理器可操作以产生触发相应命令以从外部串行闪存中的指定地址读取数据的指令帧。 串行闪存接口接收并处理指令帧，获取外部串行闪存中指定地址中包含的数据，而不管指定的地址是顺序还是非顺序，并提供数据供微处理器使用。

    Peripheral interface circuit for serial memory
    7.
    发明授权
    Peripheral interface circuit for serial memory 有权

    公开(公告)号：US10083137B2

    公开(公告)日：2018-09-25

    申请号：US14677817

    申请日：2015-04-02

    Applicant: Atmel Corporation

    Inventor： Frédéric Schumacher ,  Guillaume Pean ,  Renaud Tiennot

    IPC: G06F3/00 ,  G06F13/362 ,  G06F13/16 ,  G06F13/42

    CPC classification number: G06F13/3625 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/4282

    Abstract: A peripheral interface circuit and method is disclosed for dealing with round trip delay with serial memory. In some implementations, a finite state machine is configured to introduce a delay state prior to a read data state to absorb round trip delay associated with a memory read operation. A clock module is coupled to the finite state machine and configured to delay start of a pad return clock for the read operation until completion of the delay state. A first synchronous logic is coupled to receive the pad return clock and is configured to sample and hold data from a data bus during the read data state of the memory read operation based on the pad return clock. A second synchronous logic is coupled to receive a system clock and is configured to sample the held data based on the system clock.

    Microcontroller architecture with access stealing
    8.
    发明授权
    Microcontroller architecture with access stealing 有权

    公开(公告)号：US09626310B2

    公开(公告)日：2017-04-18

    申请号：US14835418

    申请日：2015-08-25

    Applicant: Atmel Corporation

    Inventor： Guillaume Pean ,  Renaud Tiennot ,  Vincent Debout

    IPC: G06F13/16 ,  G06F13/20 ,  G06F13/40

    CPC classification number: G06F13/1668 ,  G06F13/20 ,  G06F13/4027 ,  G06F13/4068

    Abstract: A microcontroller system is disclosed that includes an access stealing monitor coupled to a bus that is configured to receive a first access request from the bus for a first peripheral, duplicate the first access request, transform the first access request to a second access request on a second peripheral, and transfer the second access request to the bus. In another embodiment, a first peripheral coupled to the bus is configured to receive a first access request from the bus for the first peripheral, duplicate the first access request and transform the first access request to a second access request. A second peripheral coupled to the bus and to the first peripheral is configured to receive the second access request and to respond to the second access request. Methods of access stealing in a microcontroller system are also disclosed.

    PROACTIVE QUALITY OF SERVICE IN MULTI-MATRIX SYSTEM BUS
    9.
    发明申请
    PROACTIVE QUALITY OF SERVICE IN MULTI-MATRIX SYSTEM BUS 审中-公开
    多矩阵系统总线的服务质量

    公开(公告)号：US20170017593A1

    公开(公告)日：2017-01-19

    申请号：US15187619

    申请日：2016-06-20

    Applicant: Atmel Corporation

    Inventor： Franck Lunadier ,  Eric Matulik ,  Renaud Tiennot

    IPC: G06F13/362 ,  G06F13/40

    CPC classification number: G06F13/362 ,  G06F13/368 ,  G06F13/4022 ,  G06F13/4068

    Abstract: A multi-matrix bus system is disclosed that provides proactive quality of service (QoS) by propagating, as soon as possible through an arbitration node in a network transfer request path, a highest priority value coming from an upstream arbitration node or master that has a current bus request pending at the arbitration node. The bus system ensures that any last downstream arbitration node knows at any time which is the highest priority request pending in the network transfer request path from the masters that are competing to share the bus layer switches and arbitration nodes in the network transfer request path.

    Abstract translation: 公开了一种多矩阵总线系统，其通过在网络传送请求路径中通过仲裁节点尽可能快地传播来自上游仲裁节点或主机的最高优先级值来提供主动服务质量（QoS） 当前总线请求在仲裁节点挂起。 总线系统确保任何最后一个下行仲裁节点在任何时候都知道网络传输请求路径中等待的最高优先级请求是来自正在竞争共享总线层交换机和仲裁节点的网络传输请求路径中的主机。

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