公开(公告)号：US07505312B2

公开(公告)日：2009-03-17

申请号：US11447963

申请日：2006-06-07

申请人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Atsuhiro Sato ,  Makoto Sakuma ,  Masato Endo ,  Kiyohito Nishihara ,  Keiji Shuto ,  Naohisa Iino

发明人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Atsuhiro Sato ,  Makoto Sakuma ,  Masato Endo ,  Kiyohito Nishihara ,  Keiji Shuto ,  Naohisa Iino

IPC分类号： G11C16/10

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： There is disclosed a semiconductor integrated circuit device including a memory cell array having a plurality of blocks, a first non-volatile semiconductor memory cell which is arranged in the memory cell array and has an electric charge storage layer, and a second non-volatile semiconductor memory cell which is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell and has an electric charge storage layer. Regular data writing is performed with respect to the second non-volatile semiconductor memory cell after regular data writing is carried out with respect to the first non-volatile semiconductor memory cell. Additional data writing is performed with respect to the first non-volatile semiconductor memory cell after regular data writing is carried out with respect to the second non-volatile semiconductor memory cell.

摘要翻译： 公开了一种包括具有多个块的存储单元阵列的半导体集成电路器件，布置在存储单元阵列中并具有电荷存储层的第一非易失性半导体存储单元和第二非易失性半导体 存储单元，布置在与第一非易失性半导体存储单元相邻的存储单元阵列中，并具有电荷存储层。 在相对于第一非易失性半导体存储单元执行常规数据写入之后，相对于第二非易失性半导体存储单元执行正常数据写入。 在相对于第二非易失性半导体存储单元执行常规数据写入之后，相对于第一非易失性半导体存储单元执行附加数据写入。

公开(公告)号：US07122430B2

公开(公告)日：2006-10-17

申请号：US11311262

申请日：2005-12-20

申请人： Atsuhiro Sato ,  Makoto Sakuma ,  Fumitaka Arai

发明人： Atsuhiro Sato ,  Makoto Sakuma ,  Fumitaka Arai

IPC分类号： H01I21/336 ,  H01I21/8238

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529

摘要： The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-electrode dielectric. A select transistor has a second cell site gate insulator having a same thickness as the first cell site gate insulator, a second lower conductive layer on the second cell site gate insulator, a second inter-electrode dielectric on the second lower conductive layer, and a second upper conductive layer on the second inter-electrode dielectric. The peripheral transistor has a first peripheral site gate insulator having a thickness thinner than the first cell site gate insulator.

公开(公告)号：US20070177431A1

公开(公告)日：2007-08-02

申请号：US11447963

申请日：2006-06-07

申请人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Atsuhiro Sato ,  Makoto Sakuma ,  Masato Endo ,  Kiyohito Nishihara ,  Keiji Shuto ,  Naohisa Iino

发明人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Atsuhiro Sato ,  Makoto Sakuma ,  Masato Endo ,  Kiyohito Nishihara ,  Keiji Shuto ,  Naohisa Iino

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： There is disclosed a semiconductor integrated circuit device including a memory cell array having a plurality of blocks, a first non-volatile semiconductor memory cell which is arranged in the memory cell array and has an electric charge storage layer, and a second non-volatile semiconductor memory cell which is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell and has an electric charge storage layer. Regular data writing is performed with respect to the second non-volatile semiconductor memory cell after regular data writing is carried out with respect to the first non-volatile semiconductor memory cell. Additional data writing is performed with respect to the first non-volatile semiconductor memory cell after regular data writing is carried out with respect to the second non-volatile semiconductor memory cell.

摘要翻译： 公开了一种包括具有多个块的存储单元阵列的半导体集成电路器件，布置在存储单元阵列中并具有电荷存储层的第一非易失性半导体存储单元和第二非易失性半导体 存储单元，布置在与第一非易失性半导体存储单元相邻的存储单元阵列中，并具有电荷存储层。 在相对于第一非易失性半导体存储单元执行常规数据写入之后，相对于第二非易失性半导体存储单元执行正常数据写入。 在相对于第二非易失性半导体存储单元执行常规数据写入之后，相对于第一非易失性半导体存储单元执行附加数据写入。

公开(公告)号：US20060097307A1

公开(公告)日：2006-05-11

申请号：US11311262

申请日：2005-12-20

申请人： Atsuhiro Sato ,  Makoto Sakuma ,  Fumitaka Arai

发明人： Atsuhiro Sato ,  Makoto Sakuma ,  Fumitaka Arai

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529

摘要： The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-electrode dielectric. A select transistor has a second cell site gate insulator having a same thickness as the first cell site gate insulator, a second lower conductive layer on the second cell site gate insulator, a second inter-electrode dielectric on the second lower conductive layer, and a second upper conductive layer on the second inter-electrode dielectric. The peripheral transistor has a first peripheral site gate insulator having a thickness thinner than the first cell site gate insulator.

摘要翻译： 存储单元晶体管具有第一单元位置栅绝缘体，第一单元位栅极绝缘体上的第一下导电层，第一下导电层上的第一电极间电介质，以及第一电极上的第一上导电层 电介质。 选择晶体管具有与第一单元位置栅绝缘体相同厚度的第二单元位栅极绝缘体，第二单元位栅极绝缘体上的第二下导电层，第二下导电层上的第二电极间电介质，以及 在第二电极间电介质上的第二上导电层。 外围晶体管具有第一外围栅极绝缘体，该第一外围栅极绝缘体具有比第一栅极绝缘体更薄的厚度。

公开(公告)号：US07012295B2

公开(公告)日：2006-03-14

申请号：US10878372

申请日：2004-06-29

申请人： Atsuhiro Sato ,  Makoto Sakuma ,  Fumitaka Arai

发明人： Atsuhiro Sato ,  Makoto Sakuma ,  Fumitaka Arai

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529

摘要： The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-electrode dielectric. A select transistor has a second cell site gate insulator having a same thickness as the first cell site gate insulator, a second lower conductive layer on the second cell site gate insulator, a second inter-electrode dielectric on the second lower conductive layer, and a second upper conductive layer on the second inter-electrode dielectric. The peripheral transistor has a first peripheral site gate insulator having a thickness thinner than the first cell site gate insulator.

摘要翻译： 存储单元晶体管具有第一单元位置栅绝缘体，第一单元位栅极绝缘体上的第一下导电层，第一下导电层上的第一电极间电介质，以及第一电极上的第一上导电层 电介质。 选择晶体管具有与第一单元位置栅绝缘体相同厚度的第二单元位栅极绝缘体，第二单元位栅极绝缘体上的第二下导电层，第二下导电层上的第二电极间电介质，以及 在第二电极间电介质上的第二上导电层。 外围晶体管具有第一外围栅极绝缘体，该第一外围栅极绝缘体具有比第一栅极绝缘体更薄的厚度。

公开(公告)号：US20050029573A1

公开(公告)日：2005-02-10

申请号：US10878372

申请日：2004-06-29

申请人： Atsuhiro Sato ,  Makoto Sakuma ,  Fumitaka Arai

发明人： Atsuhiro Sato ,  Makoto Sakuma ,  Fumitaka Arai

IPC分类号： H01L21/8234 ,  H01L21/336 ,  H01L21/44 ,  H01L21/8247 ,  H01L27/088 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529

摘要： The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-electrode dielectric. A select transistor has a second cell site gate insulator having a same thickness as the first cell site gate insulator, a second lower conductive layer on the second cell site gate insulator, a second inter-electrode dielectric on the second lower conductive layer, and a second upper conductive layer on the second inter-electrode dielectric. The peripheral transistor has a first peripheral site gate insulator having a thickness thinner than the first cell site gate insulator.

摘要翻译： 存储单元晶体管具有第一单元位置栅绝缘体，第一单元位栅极绝缘体上的第一下导电层，第一下导电层上的第一电极间电介质，以及第一电极上的第一上导电层 电介质。 选择晶体管具有与第一单元位置栅绝缘体相同厚度的第二单元位栅极绝缘体，第二单元位栅极绝缘体上的第二下导电层，第二下导电层上的第二电极间电介质，以及 在第二电极间电介质上的第二上导电层。 外围晶体管具有第一外围栅极绝缘体，该第一外围栅极绝缘体具有比第一栅极绝缘体更薄的厚度。

公开(公告)号：US07528046B2

公开(公告)日：2009-05-05

申请号：US11676814

申请日：2007-02-20

申请人： Masayuki Ichige ,  Makoto Sakuma ,  Fumitaka Arai

发明人： Masayuki Ichige ,  Makoto Sakuma ,  Fumitaka Arai

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/3205

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/0638

摘要： A method for manufacturing a semiconductor device including a substrate, a memory cell region including first pattern, first guard ring around the memory cell, second guard ring around the first guard ring, an isolation region between the first and second guard ring, and a peripheral circuit region around the second guard ring and including second pattern, the method including exposing the resist film by multiple exposure including first and second exposures for forming latent images corresponding to the first and second patterns, a boundary area of the multiple exposure being set on the isolation region, on the first or second guard ring, or on an area between the first guard ring and the memory cell region, forming a resist pattern by developing the resist film, and etching the substrate with the resist pattern as a mask.

摘要翻译： 一种半导体器件的制造方法，包括：衬底，包括第一图案的存储单元区域，存储单元周围的第一保护环，第一保护环周围的第二保护环，第一和第二保护环之间的隔离区域， 电路区域，并且包括第二图案，所述方法包括通过多次曝光曝光所述抗蚀剂膜，所述多次曝光包括用于形成对应于所述第一和第二图案的潜像的第一和第二曝光，所述多次曝光的边界区域设置在 在第一或第二保护环上或第一保护环和存储单元区域之间的区域上，通过显影抗蚀剂膜形成抗蚀剂图案，并用抗蚀剂图案作为掩模蚀刻基板。

公开(公告)号：US20080251881A1

公开(公告)日：2008-10-16

申请号：US12143597

申请日：2008-06-20

申请人： Makoto Sakuma ,  Yasuhiko Matsunaga ,  Fumitaka Arai ,  Kikuko Sugimae

发明人： Makoto Sakuma ,  Yasuhiko Matsunaga ,  Fumitaka Arai ,  Kikuko Sugimae

IPC分类号： H01L29/00

CPC分类号： H01L27/115 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.

摘要翻译： 一种半导体器件，包括第一绝缘层，第二绝缘层，第一阻挡膜，第二阻挡膜，扩散层。 该装置还包括上接触孔，下接触孔和接触塞。 上接触孔穿透第二绝缘层，并且在第二阻挡膜中具有底部。 底部的宽度大于在与沟槽宽度方向交叉的方向上测量的在第一绝缘层中形成的沟槽。 下接触孔穿过第一绝缘层和第一阻挡膜，经由沟槽与第一接触孔连通并设置在扩散层上。 下接触孔的上部具有与沟槽相同的宽度。 接触塞设置在上接触孔和下接触孔中。

公开(公告)号：US07382649B2

公开(公告)日：2008-06-03

申请号：US11148336

申请日：2005-06-09

申请人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Makoto Sakuma ,  Tadashi Iguchi ,  Hisashi Watanobe ,  Hiroaki Tsunoda

发明人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Makoto Sakuma ,  Tadashi Iguchi ,  Hisashi Watanobe ,  Hiroaki Tsunoda

IPC分类号： G11C11/34

CPC分类号： H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile semiconductor memory includes memory cell units, each having memory cell transistors aligned in a column direction and capable of writing and erasing electronic data; and contacts on active areas, arranged on both sides of memory cell unit arrays in which the memory cell units are serially connected in the column direction, and the contacts on active areas are shared by the memory cell unit arrays; wherein, the respective memory cell unit arrays are located having a periodical shift length equal to and or more than the integral multiple length of the periodical length of the memory cell units aligned in the column direction so as to be staggered from each other as compared with neighboring memory cell unit arrays aligned in the row direction.

摘要翻译： 非易失性半导体存储器包括存储单元单元，每个存储单元单元具有在列方向上排列的存储单元晶体管，并且能够写入和擦除电子数据; 以及布置在存储单元单元在列方向上串联连接的存储单元单元阵列的两侧的有源区上的触点，并且有源区上的触点由存储单元单元阵列共享; 其中，各个存储单元单元阵列的周期性移位长度等于或大于沿列方向排列的存储单元单元的周期长度的整数倍长度，以便与第 相邻的存储单元单元阵列在行方向上排列。

公开(公告)号：US07149116B2

公开(公告)日：2006-12-12

申请号：US11337653

申请日：2006-01-24

申请人： Makoto Sakuma ,  Fumitaka Arai ,  Riichiro Shirota ,  Yasuhiko Matsunaga

发明人： Makoto Sakuma ,  Fumitaka Arai ,  Riichiro Shirota ,  Yasuhiko Matsunaga

IPC分类号： G11C11/34

CPC分类号： G11C16/10

摘要： A semiconductor memory has a memory cell matrix including a plurality of first and second cell columns alternately arranged along a row-direction, each of cell columns is implemented by a plurality of memory cell transistors, and peripheral circuits configured to drive the memory cell matrix and to read information from the memory cell matrix. The peripheral circuit encompasses (a) a leading program circuit configured to write first data into memory cell transistors in the first cell columns, (b) a lagging program circuit configured to write second data into memory cell transistors in the second cell columns after the first data are written, and (c) a voltage controller configured to control variation of threshold voltages for the memory cell transistors of the first cell columns.