公开(公告)号：US08890105B2

公开(公告)日：2014-11-18

申请号：US13687737

申请日：2012-11-28

申请人： Kiyohito Nishihara

发明人： Kiyohito Nishihara

IPC分类号： H01L29/02 ,  H01L45/00 ,  H01L27/24

CPC分类号： H01L45/00 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/1273 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/1675

摘要： A nonvolatile memory according to an embodiment includes a first wiring line; a second wiring line arranged above the first wiring line and extending in a direction crossing the first wiring line; and a resistance change layer arranged in an intersection region of the first wiring line the second wiring line, the second wiring line including a first member extending in the direction in which the second wiring line extends, and an electrode layer containing a metal element arranged on a side surface of the first member along the direction in which the second wiring line extends, a lower surface of the electrode layer being in contact with an upper surface of the resistance change layer.

摘要翻译： 根据实施例的非易失性存储器包括第一布线; 布置在所述第一布线之上并沿与所述第一布线相交的方向延伸的第二布线; 以及电阻变化层，其布置在所述第一布线与所述第二布线的交叉区域中，所述第二布线包括沿着所述第二布线延伸的方向延伸的第一构件和包含布置在所述第二布线上的金属元件的电极层 第一构件的沿着第二布线延伸的方向的侧表面，电极层的下表面与电阻变化层的上表面接触。

公开(公告)号：US20130248803A1

公开(公告)日：2013-09-26

申请号：US13601200

申请日：2012-08-31

申请人： Kiyohito NISHIHARA ,  Tetsuya HAYASHI

发明人： Kiyohito NISHIHARA ,  Tetsuya HAYASHI

IPC分类号： H01L45/00

CPC分类号： H01L45/142 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/71 ,  G11C2213/79 ,  H01L45/1608 ,  H01L51/0591

摘要： According to one embodiment, a molecular memory includes a first electrode, a second electrode, and a resistance-change molecular chain provided between the first electrode and the second electrode. The first electrode includes a core made of a first conductive material, and a side wall made of a second conductive material different from the first conductive material. The side wall is formed on a side surface of the core. The second electrode is made of a third conductive material different from the first conductive material. The resistance-change molecular chain is bonded to the first conductive material.

摘要翻译： 根据一个实施例，分子存储器包括设置在第一电极和第二电极之间的第一电极，第二电极和电阻变化分子链。 第一电极包括由第一导电材料制成的芯和由与第一导电材料不同的第二导电材料制成的侧壁。 侧壁形成在芯的侧表面上。 第二电极由不同于第一导电材料的第三导电材料制成。 电阻变化分子链与第一导电材料结合。

公开(公告)号：US08421234B2

公开(公告)日：2013-04-16

申请号：US12833329

申请日：2010-07-09

申请人： Kiyohito Nishihara

发明人： Kiyohito Nishihara

IPC分类号： H01L23/48

CPC分类号： H01L21/76816 ,  H01L21/76843 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to an embodiment of the present invention includes a substrate, isolation layers and active regions formed in the substrate, and arranged alternately along a first direction parallel to a surface of the substrate, an inter layer dielectric formed on the isolation layers and the active regions, and having holes for respective contact plugs on the respective active regions, barrier layers formed in the holes, each of the barrier layers being formed on a top surface of an active region exposed in a hole and on one of two side surfaces of the hole, the two side surfaces of the hole being perpendicular to the first direction, and plug material layers formed on the barrier layers in the holes.

摘要翻译： 根据本发明的实施例的半导体器件包括衬底，隔离层和形成在衬底中的有源区，并且沿着平行于衬底的表面的第一方向交替排列，形成在隔离层上的层间电介质和 有源区，并且在各个有源区上具有用于相应接触插塞的孔，形成在孔中的阻挡层，每个阻挡层形成在暴露在孔中的有源区的顶表面和两个侧表面之一 所述孔的两个侧表面垂直于所述第一方向，并且所述塞材料层形成在所述孔中的阻挡层上。

公开(公告)号：US20120211861A1

公开(公告)日：2012-08-23

申请号：US13225743

申请日：2011-09-06

申请人： Kiyohito NISHIHARA

发明人： Kiyohito NISHIHARA

IPC分类号： H01L27/115 ,  H01L21/768 ,  H01L21/762

CPC分类号： H01L27/11524 ,  H01L21/76229 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a plurality of element-separating insulators, and contacts. The plurality of element-separating insulators are formed in an upper layer portion of the semiconductor substrate. The plurality of element-separating insulators partition the upper layer portion into a plurality of active areas extending in a first direction. The contacts are connected to the active areas. A recess is made in a part in the first direction of an upper surface of each of the active areas. The recess is made across the entire active area in a second direction orthogonal to the first direction. Positions in the first direction of two of the contacts connected respectively to mutually-adjacent active areas are different from each other. One of the contacts is in contact with a side surface of the recess and not in contact with a bottom surface of the recess.

摘要翻译： 根据一个实施例，半导体存储器件包括半导体衬底，多个元件分离绝缘体和触点。 多个元件分离绝缘体形成在半导体衬底的上层部分中。 多个元件分离绝缘体将上层部分分成沿第一方向延伸的多个有效区域。 触点连接到活动区域。 在每个有源区域的上表面的第一方向上的部分中形成凹部。 在与第一方向正交的第二方向上在整个有源区域上形成凹部。 在相互相邻的有源区域分别连接的两个触点的第一方向上的位置彼此不同。 触点之一与凹部的侧表面接触并且不与凹部的底表面接触。

公开(公告)号：US20110049604A1

公开(公告)日：2011-03-03

申请号：US12839723

申请日：2010-07-20

申请人： Kiyohito NISHIHARA

发明人： Kiyohito NISHIHARA

IPC分类号： H01L29/788

CPC分类号： H01L21/76819 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11568

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: a semiconductor substrate; an element isolation insulator formed in an upper portion of the semiconductor substrate and dividing the upper portion into first and second active areas extending in a first direction; a first contact connected to the first active area; and a second contact connected to the second active area. Each of the first and second active area includes: a first portion connected to one of the first contact and the second contact; and a second portion having an upper surface being placed lower than an upper surface of the first portion. The first contact and the second contact are mutually shifted in the first direction. The first portion of the first active area is disposed adjacent to the second portion of the second active area.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括：半导体衬底; 形成在所述半导体衬底的上部并将所述上部分割成沿第一方向延伸的第一和第二有源区的元件绝缘绝缘体; 连接到第一活动区域的第一触点; 以及连接到第二活动区域的第二触点。 第一和第二有效区域中的每一个包括：连接到第一接触件和第二接触件之一的第一部件; 以及第二部分，其具有比第一部分的上表面低的上表面。 第一触点和第二触点在第一方向相互移位。 第一有效区域的第一部分被布置成与第二有效区域的第二部分相邻。

公开(公告)号：US07781807B2

公开(公告)日：2010-08-24

申请号：US11947008

申请日：2007-11-29

申请人： Kiyohito Nishihara ,  Fumitaka Arai

发明人： Kiyohito Nishihara ,  Fumitaka Arai

IPC分类号： H01L29/80

CPC分类号： H01L27/0688 ,  H01L21/8221 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551

摘要： A three-dimensional non-volatile semiconductor storage device which realizes both increased packing density and improved performance is disclosed. According to one aspect, there is provided a non-volatile semiconductor storage device comprising a first non-volatile memory cell provided on a first insulator, which includes a first semiconductor layer, and a first gate stack provided above the first semiconductor layer and including a first charge storage layer and a first control gate electrode, and a second non-volatile memory cell provided above the first non-volatile memory cell, which includes a second semiconductor layer, and a second gate stack provided above the second semiconductor layer and including a second charge storage layer and a second control gate electrode, the second gate stack being positioned to be aligned with the first gate stack, and wherein the first control gate electrode functions as a back gate electrode to the second non-volatile memory cell.

摘要翻译： 公开了一种三维非易失性半导体存储装置，其实现了增加的封装密度和改进的性能。 根据一个方面，提供了一种非易失性半导体存储装置，包括设置在第一绝缘体上的第一非易失性存储单元，第一绝缘体包括第一半导体层，以及设置在第一半导体层上方的第一栅极堆叠， 第一电荷存储层和第一控制栅电极，以及设置在第一非易失性存储单元上方的第二非易失性存储单元，其包括第二半导体层，以及设置在第二半导体层上方的第二栅极堆叠， 第二电荷存储层和第二控制栅电极，第二栅极堆叠被定位成与第一栅极堆叠对准，并且其中第一控制栅电极用作到第二非易失性存储单元的背栅电极。

公开(公告)号：US20100117135A1

公开(公告)日：2010-05-13

申请号：US12564349

申请日：2009-09-22

申请人： Makoto MIZUKAMI ,  Kiyohito Nishihara ,  Masaki Kondo ,  Takashi Izumida ,  Hirokazu Ishida ,  Atsushi Fukumoto ,  Fumiki Aiso ,  Daigo Ichinose ,  Tadashi Iguchi

发明人： Makoto MIZUKAMI ,  Kiyohito Nishihara ,  Masaki Kondo ,  Takashi Izumida ,  Hirokazu Ishida ,  Atsushi Fukumoto ,  Fumiki Aiso ,  Daigo Ichinose ,  Tadashi Iguchi

IPC分类号： H01L27/12 ,  H01L21/86

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor device is formed on a SOI substrate having a semiconductor substrate, a buried oxide film formed on the semiconductor substrate, and a semiconductor layer formed on the buried oxide film, the semiconductor substrate having a first conductive type, the semiconductor layer having a second conductive type, wherein the buried oxide film has a first opening opened therethrough for communicating the semiconductor substrate with the semiconductor layer, the semiconductor layer is arranged to have a first buried portion buried in the first opening in contact with the semiconductor substrate and a semiconductor layer main portion positioned on the first buried portion and on the buried oxide film, the semiconductor substrate has a connection layer buried in a surface of the semiconductor substrate and electrically connected to the first buried portion in the first opening, the connection layer having the second conductive type, and the semiconductor device includes a contact electrode buried in a second opening, a side surface of the contact electrode being connected to the semiconductor layer main portion, a bottom surface of the contact electrode being connected to the connection layer, the second opening passing through the semiconductor layer main portion and the buried oxide film, and the second opening reaching a surface portion of the connection layer.

摘要翻译： 半导体器件形成在具有半导体衬底的SOI衬底上，形成在半导体衬底上的掩埋氧化膜以及形成在掩埋氧化膜上的半导体层，该半导体衬底具有第一导电类型，该半导体层具有第二导电型 导电型，其中所述掩埋氧化物膜具有通过其开口的第一开口，用于使所述半导体衬底与所述半导体层连通，所述半导体层被布置为具有埋在所述第一开口中的与所述半导体衬底接触的第一掩埋部分和半导体层 主要部分位于第一掩埋部分和掩埋氧化膜上，半导体衬底具有埋在半导体衬底的表面中并与第一开口中的第一掩埋部分电连接的连接层，连接层具有第二导电 类型，并且半导体器件包括接触电极 阴极埋入第二开口中，接触电极的侧表面连接到半导体层主体部分，接触电极的底表面连接到连接层，第二开口穿过半导体层主体部分和埋设 氧化膜，第二开口到达连接层的表面部分。

公开(公告)号：US20140061565A1

公开(公告)日：2014-03-06

申请号：US13687737

申请日：2012-11-28

申请人： Kiyohito NISHIHARA

发明人： Kiyohito NISHIHARA

IPC分类号： H01L45/00

CPC分类号： H01L45/00 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/1273 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/1675

摘要： A nonvolatile memory according to an embodiment includes a first wiring line; a second wiring line arranged above the first wiring line and extending in a direction crossing the first wiring line; and a resistance change layer arranged in an intersection region of the first wiring line the second wiring line, the second wiring line including a first member extending in the direction in which the second wiring line extends, and an electrode layer containing a metal element arranged on a side surface of the first member along the direction in which the second wiring line extends, a lower surface of the electrode layer being in contact with an upper surface of the resistance change layer.

摘要翻译： 根据实施例的非易失性存储器包括第一布线; 布置在所述第一布线之上并沿与所述第一布线相交的方向延伸的第二布线; 以及电阻变化层，其布置在所述第一布线与所述第二布线的交叉区域中，所述第二布线包括沿着所述第二布线延伸的方向延伸的第一构件和包含布置在所述第二布线上的金属元件的电极层 第一构件的沿着第二布线延伸的方向的侧表面，电极层的下表面与电阻变化层的上表面接触。

公开(公告)号：US08344441B2

公开(公告)日：2013-01-01

申请号：US12839723

申请日：2010-07-20

申请人： Kiyohito Nishihara

发明人： Kiyohito Nishihara

IPC分类号： H01L29/788

CPC分类号： H01L21/76819 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11568

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: a semiconductor substrate; an element isolation insulator formed in an upper portion of the semiconductor substrate and dividing the upper portion into first and second active areas extending in a first direction; a first contact connected to the first active area; and a second contact connected to the second active area. Each of the first and second active area includes: a first portion connected to one of the first contact and the second contact; and a second portion having an upper surface being placed lower than an upper surface of the first portion. The first contact and the second contact are mutually shifted in the first direction. The first portion of the first active area is disposed adjacent to the second portion of the second active area.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括：半导体衬底; 形成在所述半导体衬底的上部并将所述上部分割成沿第一方向延伸的第一和第二有源区的元件绝缘绝缘体; 连接到第一活动区域的第一触点; 以及连接到第二活动区域的第二触点。 第一和第二有效区域中的每一个包括：连接到第一接触件和第二接触件之一的第一部件; 以及第二部分，其具有比第一部分的上表面低的上表面。 第一触点和第二触点在第一方向相互移位。 第一有效区域的第一部分被布置成与第二有效区域的第二部分相邻。

公开(公告)号：US20120018780A1

公开(公告)日：2012-01-26

申请号：US13075665

申请日：2011-03-30

申请人： Kazuaki Iwasawa ,  Shigeo Kondo ,  Hiroshi Akahori ,  Kiyohito Nishihara ,  Yingkang Zhang ,  Masaki Kondo ,  Hidenobu Nagashima ,  Takashi Ichikawa

发明人： Kazuaki Iwasawa ,  Shigeo Kondo ,  Hiroshi Akahori ,  Kiyohito Nishihara ,  Yingkang Zhang ,  Masaki Kondo ,  Hidenobu Nagashima ,  Takashi Ichikawa

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L27/11521

摘要： According to one embodiment, a method is disclosed for manufacturing a semiconductor device. A side face parallel to a channel direction of a plurality of gate electrodes provided via a gate insulating film above a semiconductor substrate is included as a part of an inner wall of an isolation groove provided between the adjacent gate electrodes. The method can include forming a protection film covering the side face of the gate electrode. The method can include etching the semiconductor substrate using the gate electrode as a mask to form the isolation groove. The side face of the gate electrode is covered with the protection film. The method can include forming a first insulating film by oxidizing a surface of the isolation groove to fill a bottom portion of the isolation groove. In addition, the method can include forming a second insulating film on the first insulating film to fill an upper portion of the isolation groove including the side face of the gate electrode.

摘要翻译： 根据一个实施例，公开了一种用于制造半导体器件的方法。 作为设置在相邻栅电极之间的隔离槽的内壁的一部分，包括平行于通过半导体基板上方的栅极绝缘膜设置的多个栅电极的沟道方向的侧面。 该方法可以包括形成覆盖栅电极的侧面的保护膜。 该方法可以包括使用栅电极作为掩模来蚀刻半导体衬底以形成隔离槽。 栅电极的侧面被保护膜覆盖。 该方法可以包括通过氧化隔离槽的表面来填充隔离槽的底部来形成第一绝缘膜。 此外，该方法可以包括在第一绝缘膜上形成第二绝缘膜以填充包括栅电极的侧面的隔离槽的上部。