公开(公告)号：US4260909A

公开(公告)日：1981-04-07

申请号：US937951

申请日：1978-08-30

申请人： Austin C. Dumbri ,  Walter Rosenzweig

发明人： Austin C. Dumbri ,  Walter Rosenzweig

IPC分类号： G05F3/20 ,  G11C11/407 ,  G11C11/413 ,  G11C11/417 ,  H01L21/822 ,  H01L27/04 ,  H03K3/011 ,  H03K3/356 ,  H03K3/35 ,  H03K3/353 ,  H03L1/00

CPC分类号： G05F3/205 ,  G11C11/417 ,  H01L27/04 ,  H03K3/011 ,  H03K3/356008

摘要： A back gate bias voltage generator circuit consists of three MOS transistors (Q4, Q5, Q6) with a separate load element (Q1, Q2, Q3) coupled to the drain of each and a voltage clamp (Q7) connected to an output terminal (16). A terminal at the potential of a power supply (VCC) serves as one input and a terminal at the substrate potential (VSub) serves as another input. When the power supply (VCC) potential and the substrate potential are within normal operating ranges, the output terminal (16) assumes a reference potential (VSS). The potential of the output terminal increases in magnitude if either of the two input potentials (VSS, VSub) goes outside preselected operating ranges.

摘要翻译： 背栅偏置电压发生器电路由三个MOS晶体管（Q4，Q5，Q6）组成，具有耦合到每个的漏极的单独的负载元件（Q1，Q2，Q3）和连接到输出端子的电压钳（Q7） 16）。 电源电位（VCC）的端子用作一个输入，并且在衬底电位（VSub）上的端子用作另一个输入。 当电源（VCC）电位和衬底电位在正常工作范围内时，输出端（16）呈现参考电位（VSS）。 如果两个输入电位（VSS，VSub）中的任一个超出了预选的工作范围，输出端子的电位就会增加。

公开(公告)号：US4284905A

公开(公告)日：1981-08-18

申请号：US44397

申请日：1979-05-31

申请人： Walter Rosenzweig

发明人： Walter Rosenzweig

IPC分类号： G05F3/20 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/003 ,  H03K19/20

CPC分类号： G05F3/205 ,  H03K19/01714 ,  H03K19/018507

摘要： An improved IGFET bootstrap driver circuit capable of driving a load impedance to substantially full VDD power supply voltage and holding the load at that voltage for an indefinite period of time. The circuit includes a load transistor, a feedback capacitor connected between the source and gate electrodes of the load transistor, a fix valued resistor connected between the gate electrode of the load transistor and an on-chip bias voltage generating circuit for providing a bias voltage greater than VDD+VT. The resistor and the bias voltage generating circuit provide sufficient current to replenish the charge lost from the feedback capacitor through junction leakage currents in the driver circuit. The resistor is of a sufficiently high value such that the current drain from the generating circuit is insignificantly small in comparison to the current drain from the VDD power supply. The improved circuit also permits the load transistor to be switched "on" or "off" by an externally applied signal.

摘要翻译： 一种改进的IGFET自举驱动电路，能够将负载阻抗驱动到基本上完全的VDD电源电压，并将负载保持在该电压下无限期的时间。 电路包括负载晶体管，连接在负载晶体管的源电极和栅电极之间的反馈电容器，连接在负载晶体管的栅电极和片上偏置电压发生电路之间的固定值电阻，用于提供更大的偏置电压 比VDD + VT。 电阻器和偏置电压产生电路提供足够的电流以补充由驱动器电路中的结漏电流引起的反馈电容器损失的电荷。 电阻器具有足够高的值，使得与来自VDD电源的电流消耗相比，来自发生电路的电流漏极不显着。 改进的电路还允许负载晶体管通过外部施加的信号被“接通”或“关闭”。