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公开(公告)号：US11142825B2
公开(公告)日：2021-10-12
申请号：US16780715
申请日：2020-02-03
申请人： AVERATEK CORPORATION
发明人： Sunity K. Sharma , Shinichi Iketani
摘要： Methods, systems, and apparatus for coating the internal surface of nano-scale cavities on a substrate are contemplated. A first fluid of high wettability is applied to the nano-scale cavity, filling the cavity. A second fluid carrying a conductor or a catalyst is applied over the opening of the nano-scale cavity. The second fluid has a lower vapor pressure than the first fluid. The first fluid is converted to a gas, for example by heating the substrate. The gas exits the nano-scale cavity, creating a negative pressure or vacuum in the nano-scale cavity. The negative pressure draws the second fluid into the nano-scale cavity. The conductor is deposited on the interior surface of the nano-scale cavity, preferably less than 10 nm thick.
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公开(公告)号：US11716819B2
公开(公告)日：2023-08-01
申请号：US16449202
申请日：2019-06-21
申请人： AVERATEK CORPORATION
CPC分类号： H05K3/424 , C25D7/00 , H05K3/0023 , H05K3/0044 , H05K3/425 , H05K2203/0723
摘要： The present invention relates to methods and systems for deposition of metal conductors using asymmetrical electrolytic plating, in which one surface (e.g., top) of a substrate is coated with an electrical conductor, and an opposite (e.g., bottom, or other) surface of which is not coated. A channel is formed between the two sides of the substrate, passing through the substrate and, in some embodiments, passing through the conductor. Electrolytic plating is performed such that metal is deposited from the edge of the conduct proximal to the channel, along the side walls of the channel, and up to, and in some embodiments on to, the other side of the substrate. Use of etching or plate resist layers are also contemplated.
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公开(公告)号：US20190394888A1
公开(公告)日：2019-12-26
申请号：US16448973
申请日：2019-06-21
申请人： AVERATEK CORPORATION
摘要： The present invention relates to methods and systems that utilize a catalyst or thin metal film by atomic level deposition (ALD) of one or more metals that allows fine traces deposition to the trench formed in a dielectric material, thereby minimizing potential physical damage due to embedded conductor format and making the fine space between traces to prevent electromigration in the traces.
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公开(公告)号：US20220418113A1
公开(公告)日：2022-12-29
申请号：US17896893
申请日：2022-08-26
申请人： AVERATEK CORPORATION
摘要： Various inventions are disclosed in the microchip manufacturing arts. Conductive pattern formation by semi-additive processes are disclosed. Further conductive patterns and methods using activated precursors are also disclosed. Aluminum laminated surfaces and methods of circuit formation therefrom are further disclosed. Circuits formed on an aluminum heat sink are also disclosed. The inventive subject matter further discloses methods of electrolytic plating by controlling surface area of an anode.
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公开(公告)号：US11076492B2
公开(公告)日：2021-07-27
申请号：US16717719
申请日：2019-12-17
申请人： AVERATEK CORPORATION
摘要： Devices, methods, and systems for forming an electrical circuit out of a conductor embedded in two layers of substrate are disclosed. Portions of the two layers of substrate and the conductor are removed, forming a cavity through the two layers and the conductor. A blocker material is deposited along the wall of the cavity. A portion of the blocker material and adjacent layer of the substrate is removed forming another cavity in contact with a part of the conductor. A surface of the second cavity is then electroless plated by a conductive metal to form part of the electrical circuit.
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公开(公告)号：US20190394887A1
公开(公告)日：2019-12-26
申请号：US16449202
申请日：2019-06-21
申请人： AVERATEK CORPORATION
摘要： The present invention relates to methods and systems for deposition of metal conductors using asymmetrical electrolytic plating, in which one surface (e.g., top) of a substrate is coated with an electrical conductor, and an opposite (e.g., bottom, or other) surface of which is not coated. A channel is formed between the two sides of the substrate, passing through the substrate and, in some embodiments, passing through the conductor. Electrolytic plating is performed such that metal is deposited from the edge of the conduct proximal to the channel, along the side walls of the channel, and up to, and in some embodiments on to, the other side of the substrate. Use of etching or plate resist layers are also contemplated.
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公开(公告)号：US12063748B2
公开(公告)日：2024-08-13
申请号：US17174759
申请日：2021-02-12
申请人： AVERATEK CORPORATION
CPC分类号： H05K3/181 , C23C18/1605 , C23F17/00 , H05K3/285 , H05K3/4644 , H05K2203/0307
摘要： Systems, methods, and devices related to catalyzed metal foils are disclosed. Contemplated metal foils have a bottom surface, preferably roughened to Ra of at least 0.1 μm, bearing a catalyst material. The metal foils are etchable, typically of aluminum or derivative thereof, and is less than 500 μm thick. Methods and systems for forming circuits from catalyzed metal foils are also disclosed. The catalyst material bearing surface of the metal foil is applied to a substrate and laminated, in some embodiments with a thermoset resin or thermoplastic resin therebetween or an organic material first coating the catalytic material. The metal foil is removed to expose the catalyst material, and a conductor is plated to the catalyst material.
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公开(公告)号：US20230345642A1
公开(公告)日：2023-10-26
申请号：US18214391
申请日：2023-06-26
申请人： AVERATEK CORPORATION
CPC分类号： H05K3/424 , H05K3/0023 , C25D7/00 , H05K3/425 , H05K3/0044 , H05K2203/0723
摘要： The present invention relates to methods and systems for deposition of metal conductors using asymmetrical electrolytic plating, in which one surface (e.g., top) of a substrate is coated with an electrical conductor, and an opposite (e.g., bottom, or other) surface of which is not coated. A channel is formed between the two sides of the substrate, passing through the substrate and, in some embodiments, passing through the conductor. Electrolytic plating is performed such that metal is deposited from the edge of the conduct proximal to the channel, along the side walls of the channel, and up to, and in some embodiments on to, the other side of the substrate. Use of etching or plate resist layers are also contemplated.
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公开(公告)号：US20210307177A1
公开(公告)日：2021-09-30
申请号：US17344288
申请日：2021-06-10
申请人： AVERATEK CORPORATION
摘要： Various inventions are disclosed in the microchip manufacturing arts. Conductive pattern formation by semi-additive processes are disclosed. Further conductive patterns and methods using activated precursors are also disclosed. Aluminum laminated surfaces and methods of circuit formation therefrom are further disclosed. Circuits formed on an aluminum heat sink are also disclosed. The inventive subject mater further discloses methods of electrolytic plating by controlling surface area of an anode.
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公开(公告)号：US11877404B2
公开(公告)日：2024-01-16
申请号：US17208890
申请日：2021-03-22
申请人： AVERATEK CORPORATION
发明人： Shinichi Iketani
CPC分类号： H05K3/4652 , H05K3/0041 , H05K3/062 , H05K3/185 , H05K2201/0358 , H05K2203/0323 , H05K2203/0376 , H05K2203/0582 , H05K2203/06
摘要： Systems, methods, and devices related to catalyzed metal foils are disclosed. Contemplated metal foils have a bottom surface, preferably roughened to Ra of at least 0.1 μm, bearing a catalyst material. The metal foils are etchable, typically of aluminum or derivative thereof, and is less than 500 μm thick. Methods and systems for forming circuits from catalyzed metal foils are also disclosed. The catalyst material bearing surface of the metal foil is applied to a substrate and laminated, in some embodiments with a thermoset resin or thermoplastic resin therebetween or an organic material first coating the catalytic material. The metal foil is removed to expose the catalyst material, and a conductor is plated to the catalyst material.
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