公开(公告)号：US20120081832A1

公开(公告)日：2012-04-05

申请号：US13305181

申请日：2011-11-28

Applicant: Azuma Chikara

Inventor： Azuma Chikara

IPC: H01G4/30

CPC classification number: H05K3/303 ,  H01G2/065 ,  H01G4/06 ,  H01G4/30 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/30105 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/181 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/10643 ,  H05K2201/10674 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A capacitive precursor includes electrically conductive material layers stacked on a substrate. The electrically conductive layers provide first and second patterns. The patterns each include overlaying areas free of the electrically conductive material. The first pair of areas overlay areas of the second pattern having the electrically conductive material and the second pair of areas overlay areas of the first pattern having the electrically conductive material. Dielectric layers are interposed between neighboring electrically conductive material layers for electrical isolation. One or more capacitive precursors can be dropped onto or into a board and during assembly of a packaged semiconductor device and have electrically conducting layers associated with its respective plates connected together to form a capacitor during assembly using conventional assembly steps.

Abstract translation: 电容性前体包括层叠在基板上的导电材料层。 导电层提供第一和第二图案。 这些图案各自包括没有导电材料的覆盖区域。 第一对区域覆盖具有导电材料的第二图案的区域，并且第二对区域覆盖具有导电材料的第一图案的区域。 电介质层介于相邻的导电材料层之间用于电隔离。 一个或多个电容性前体可以掉落到板上或者在组装封装的半导体器件期间并且具有与其相应的板连接在一起的导电层，以在组装期间使用传统的组装步骤形成电容器。

公开(公告)号：US09119321B2

公开(公告)日：2015-08-25

申请号：US13305196

申请日：2011-11-28

Applicant: Azuma Chikara

Inventor： Azuma Chikara

IPC: H01G7/00 ,  H05K1/18 ,  H01G2/06 ,  H01G4/06 ,  H01G4/30 ,  H01L23/498 ,  H01L23/50 ,  H05K1/02 ,  H05K1/16 ,  H01L23/00 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/303 ,  H01G2/065 ,  H01G4/06 ,  H01G4/30 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/30105 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/181 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/10643 ,  H05K2201/10674 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of assembling a packaged semiconductor device includes dropping a pre-formed capacitor precursor and an integrated circuit on a surface of a substrate. A pair of vias are formed in the pre-formed capacitor precursor if they don't already exist. The vias are filled with an electrically conductive material to form a chip capacitor. The filling of the vias provides an electrical contact between capacitor plates of the chip capacitor and electrically conductive contact regions on the substrate.

Abstract translation: 一种组装封装半导体器件的方法包括将预先形成的电容器前体和集成电路放在衬底的表面上。 如果它们不存在，则在预先形成的电容器前体中形成一对通孔。 通孔填充有导电材料以形成片状电容器。 通孔的填充提供了片状电容器的电容器板和衬底上的导电接触区域之间的电接触。

公开(公告)号：US20120079717A1

公开(公告)日：2012-04-05

申请号：US13305196

申请日：2011-11-28

Applicant: Azuma Chikara

Inventor： Azuma Chikara

IPC: H05K3/30

CPC classification number: H05K3/303 ,  H01G2/065 ,  H01G4/06 ,  H01G4/30 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/30105 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/181 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/10643 ,  H05K2201/10674 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of assembling a packaged semiconductor device includes dropping a pre-formed capacitor precursor on a surface of a substrate. A pair of vias are formed in the pre-formed capacitor precursor if they don't already exist. The vias are filled with an electrically conductive material to form a chip capacitor. The filling of the vias provides an electrical contact between capacitor plates of the chip capacitor and electrically conductive contact regions on the substrate.

Abstract translation: 组装封装的半导体器件的方法包括将预先形成的电容器前体放在衬底的表面上。 如果它们不存在，则在预先形成的电容器前体中形成一对通孔。 通孔填充有导电材料以形成片状电容器。 通孔的填充提供了片状电容器的电容器板和衬底上的导电接触区域之间的电接触。

公开(公告)号：US20090296310A1

公开(公告)日：2009-12-03

申请号：US12132316

申请日：2008-06-03

Applicant: Azuma Chikara

Inventor： Azuma Chikara

IPC: H05K1/18 ,  H01G4/30 ,  H01L21/50

CPC classification number: H05K3/303 ,  H01G2/065 ,  H01G4/06 ,  H01G4/30 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/30105 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/181 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/10643 ,  H05K2201/10674 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A capacitive precursor (100) and packaged semiconductor devices therefrom includes a substrate (105), a plurality of electrically conductive material layers (111-118) stacked on the substrate (105). The plurality of electrically conductive layers (111-118) provide first and second patterns (200 and 250). The first patterns (200) each include at least a first pair of overlaying areas free of the electrically conductive material, and the second patterns (250) each include at least a second pair of overlaying areas free of the electrically conductive material. The first pair of areas overlay areas of the second pattern having the electrically conductive material and the second pair of areas overlay areas of the first pattern having the electrically conductive material. A plurality of dielectric layers (101-107) are interposed between neighboring electrically conductive material layers (111-118) for electrical isolation. One or more capacitive precursors can be dropped onto or into a board and during assembly of a packaged semiconductor device and have electrically conducting layers associated with its respective plates connected together to form a capacitor during assembly using conventional assembly steps.

Abstract translation: 电容前驱体（100）及其封装的半导体器件包括衬底（105），堆叠​​在衬底（105）上的多个导电材料层（111-118）。 多个导电层（111-118）提供第一和第二图案（200和250）。 第一图案（200）各自包括至少第一对无导电材料的重叠区域，并且第二图案（250）各自包括至少第二对不含导电材料的重叠区域。 第一对区域覆盖具有导电材料的第二图案的区域，并且第二对区域覆盖具有导电材料的第一图案的区域。 在相邻的导电材料层（111-118）之间插入多个电介质层（101-107），用于电隔离。 一个或多个电容性前体可以掉落到基板上或者在组装封装的半导体器件期间并且具有与连接在一起的相应板相关联的导电层，以在组装期间使用传统的组装步骤形成电容器。