公开(公告)号：US09502269B2

公开(公告)日：2016-11-22

申请号：US14676503

申请日：2015-04-01

Applicant: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC.

Inventor： Alan M. Berard ,  John A. Hughes ,  Keith K. Sturcken ,  Timothy Whalen

IPC: H01L21/50 ,  H01L23/36 ,  H01L23/10 ,  H01L23/427

CPC classification number: H01L21/50 ,  H01L23/10 ,  H01L23/36 ,  H01L23/427 ,  H01L2924/0002 ,  Y10T29/49353 ,  H01L2924/00

Abstract: An apparatus for cooling electronic devices to be used in the vacuum of space is described. a window frame is provided as packaging for an electronic device having a substrate and a chip. The window frame includes an opening to allow a heat pipe to be in direct contact with a backside of the chip. The window frame is hermetically sealed to the backside of the chip. The window frame is also welded to a kovar ring located on the backside of the chip to provide a hermetic seal between the window frame and the substrate.

Abstract translation: 描述用于冷却在空间真空中使用的电子装置的装置。 提供了一种用于具有基板和芯片的电子设备的封装的窗框。 窗框包括允许热管与芯片的背面直接接触的开口。 窗框被密封到芯片的背面。 窗框还焊接到位于芯片背面的科瓦环，以在窗框和基板之间提供气密密封。

公开(公告)号：US20130309815A1

公开(公告)日：2013-11-21

申请号：US13951502

申请日：2013-07-26

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： John A. Hughes ,  Christy A. Hagerty ,  Santos Nazario-Camacho ,  Keith K. Sturcken

IPC: H01L21/50

CPC classification number: H01L21/50 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/562 ,  H01L2224/13 ,  H01L2924/14

Abstract: An electronic device package includes a substrate and wire columns arranged in groups about a neutral stress point of the substrate. The height of the wire columns is substantially uniform for the plural groups of wire columns, and a length of at least one of the wire columns is greater than the uniform height. A method of fabricating an electronic device package having a column grid array includes applying two templates on wire columns of the column grid array and bending at least one wire column to increase its length while maintaining a uniform height for the column grid array. In another aspect, an electronic device package substrate includes wire columns having at least one non-uniformity in lengths of the columns, and the length of a wire column corresponds to a distance of that wire column from the neutral stress point of the substrate. The non-uniformity of length in the wire columns reduces stress in the package leads after attachment of the package to a carrier substrate, such as a printed circuit board.

Abstract translation: 一种电子器件封装，包括基板和布置成围绕基板的中性应力点组成的线柱。 线列的高度对于多组线柱而言基本上是均匀的，并且线柱中的至少一个的长度大于均匀的高度。 一种制造具有列栅格阵列的电子器件封装的方法，包括在列格栅阵列的线柱上施加两个模板，并弯曲至少一个线柱以增加其长度，同时保持柱格阵列的均匀高度。 在另一方面，一种电子器件封装衬底包括具有柱长度至少一个不均匀性的线柱，并且线柱的长度对应于该线柱与衬底的中性应力点的距离。 电线柱中的长度不均匀性降低了将封装件附接到诸如印刷电路板的载体衬底之后的封装引线中的应力。

公开(公告)号：US08586417B1

公开(公告)日：2013-11-19

申请号：US13951502

申请日：2013-07-26

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： John A. Hughes ,  Christy A. Hagerty ,  Santos Nazario-Camacho ,  Keith K. Sturcken

IPC: H01L23/49

CPC classification number: H01L21/50 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/562 ,  H01L2224/13 ,  H01L2924/14

Abstract: An electronic device package includes a substrate and wire columns arranged in groups about a neutral stress point of the substrate. The height of the wire columns is substantially uniform for the plural groups of wire columns, and a length of at least one of the wire columns is greater than the uniform height. A method of fabricating an electronic device package having a column grid array includes applying two templates on wire columns of the column grid array and bending at least one wire column to increase its length while maintaining a uniform height for the column grid array. In another aspect, an electronic device package substrate includes wire columns having at least one non-uniformity in lengths of the columns, and the length of a wire column corresponds to a distance of that wire column from the neutral stress point of the substrate. The non-uniformity of length in the wire columns reduces stress in the package leads after attachment of the package to a carrier substrate, such as a printed circuit board.

公开(公告)号：US20140175675A1

公开(公告)日：2014-06-26

申请号：US14191592

申请日：2014-02-27

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Keith K. Sturcken ,  John A. Hughes ,  Thomas E. Love ,  Sheila J. Konecke ,  Jeffrey Montag ,  Peter M. Wallace

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  G01R31/003 ,  G01R31/2849 ,  G01R31/2855 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/15331

Abstract: A method for manufacturing an electronic multi-chip module that involves stacking at least six tested devices to form the module. These devices may be individually tested prior to assembling the electronic module. After individually testing the devices, the devices may be stacked one on top of the other to form an electronic multi-chip module having at least six stacked devices. Other embodiments may be described and claimed.

Abstract translation: 一种用于制造电子多芯片模块的方法，其包括堆叠至少六个被测试的装置以形成模块。 这些设备可以在组装电子模块之前单独测试。 在对设备进行单独测试之后，可以将设备堆叠在一起而形成具有至少六个堆叠设备的电子多芯片模块。 可以描述和要求保护其他实施例。