公开(公告)号：US20130341644A1

公开(公告)日：2013-12-26

申请号：US13879696

申请日：2012-07-18

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Robert Actis ,  Pane-chane Chao ,  Bernard J. Schmanski ,  Anthony A. Immorlica ,  Kanin Chu ,  Robert J. Lender, JR. ,  Dong Xu ,  Sue May Jessup

IPC: H01L23/373

CPC classification number: H01L23/373 ,  H01L23/481 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2224/4847 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1421 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00

Abstract: In summary, a vertical metalized transition in the form of a via goes from the back side of a high thermal conductivity substrate and through any semiconductor layers thereon to a patterned metalized strip, with the substrate having a patterned metalized layer on the back side that is provided with a keep away zone dimensioned to provide impedance matching for RF energy coupled through the substrate to the semiconductor device while at the same time permitting the heat generated by the semiconductor device to flow through the high thermal conductivity substrate, through the back side of the substrate and to a beat sink.

Abstract translation: 总而言之，以通孔形式的垂直金属化转变从高导热性衬底的背面开始并通过其上的任何半导体层到图案化的金属化带，衬底在背面具有图案化的金属化层， 具有保留区，其尺寸设置成为通过衬底耦合到半导体器件的RF能量提供阻抗匹配，同时允许由半导体器件产生的热量流过高导热性衬底，通过该衬底的背面 底物和一个水槽。