Abstract:
A diode code translator circuit is described in which inhibiting transistors are driven by coded output signals to inhibit concurrent input signals in a predetermined priority pattern. The uninhibited input signals drive an OR gate to provide a transfer signal for gating the coded output signals. A system for cascading the code translator circuits of this invention is also shown in which the transfer signals from a plurality of the code translator circuits serve as input signals to a succeeding stage. The transfer signal from the succeeding stage serves as the gating signal. In this arrangement, the coded output signals from the plurality of code translation circuits are connected in parallel to extend the priority sequence to the cascaded system.
Abstract:
A content addressable memory cell constructed from nine field effect transistors is disclosed in which the content addressing function is achieved by two of the nine field effect transistors. A memory is also disclosed to illustrate how the cell may be utilized. A second content addressable memory cell similar to the first is disclosed to show how two independent users can access the same cell.
Abstract:
A resistive read-only memory is manufactured initially with all of its resistor cross-point connections intact. Thereafter information is written into the memory by destroying selected resistor cross-point connections by applying a voltage across each row and column circuit combination uniquely defining one of the selected cross-points The voltage drives destructive current through the selected cross-points but nonselected resistor crosspoints are preserved intact by simultaneously biasing nonselected row and column circuits to respective lower voltage levels. Apparatus is also indicated for applying the aforementioned voltages.