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公开(公告)号：US12292660B2
公开(公告)日：2025-05-06
申请号：US18620022
申请日：2024-03-28
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
IPC: G02F1/1345 , G02F1/1333 , G02F1/1335 , G02F1/1343 , G02F1/1347 , G06F3/041 , G06F3/044 , H05K1/02 , H05K1/14
Abstract: A display module is provided. The display module includes: a display panel, a light control panel, at least one first circuit board for the display panel, and at least one second circuit board for the light control panel. The display panel and the light control panel) are stacked, the display panel is on a light-emitting side of the light control panel, a light-emitting surface of the display panel is on a first surface, and at least part of an orthographic projection of any one of the at least one first circuit board on the first surface does not overlap with an orthographic projection of the at least one second circuit board on the first surface in a direction perpendicular to the first surface.
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公开(公告)号：US12230184B2
公开(公告)日：2025-02-18
申请号：US17634733
申请日：2021-03-29
Inventor： Qiujie Su , Yingmeng Miao , Dongchuan Chen , Yanping Liao , Seungmin Lee , Xibin Shao , Xiaofeng Yin
Abstract: At least one chip group and a group of first PLG wirings corresponding to each of the chip groups are disposed in a first bonding area, each of the chip groups includes at least two groups of chip units, each group of the chip units includes at least one gate drive chip, each group of the first PLG wirings includes a first wiring and at least one second wiring; power pins of any two adjacent gate drive chips are connected by the first wiring, each of the second wirings surrounds and passes through each of the gate drive chips, the first wirings connected with the power pin of the last gate drive chip in the previous group of the chip units and any of the second wirings, are parallelly connected with the power pin of the first gate drive chip in the next group of the chip units.
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公开(公告)号：US20240168348A1
公开(公告)日：2024-05-23
申请号：US18425819
申请日：2024-01-29
Inventor： Wenjie Hou , Yingmeng Miao , Qiujie Su , Chongyang Zhao , Feng Qu
IPC: G02F1/1362
CPC classification number: G02F1/136286 , G02F1/136209 , G02F1/136222
Abstract: Provided are an array substrate and a manufacturing method thereof, and a display device. The array substrate includes a plurality of data lines and sub-pixels. At least one sub-pixel includes: a first insulating layer; a gate; an active layer located on one side of the first insulating layer away from the gate; a pixel electrode; a first electrode located connected to the active layer and in contact with the pixel electrode; a second electrode connected to the active layer and a data line; a second insulating layer having a first opening, wherein the orthographic projection of the first opening partially overlaps with the orthographic projections of the pixel electrode and the first electrode; a connection electrode in contact with the pixel electrode and the first electrode through the first opening; and a common electrode located on one side of the second insulating layer away from the pixel electrode.
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公开(公告)号：US11829540B2
公开(公告)日：2023-11-28
申请号：US17310984
申请日：2020-11-30
Inventor： Qiujie Su , Yanping Liao , Yingmeng Miao , Chongyang Zhao , Bo Hu , Xiaofeng Yin
IPC: G06F3/044 , G06F3/041 , G02F1/1333 , G02F1/1343 , G02F1/1362 , H01L27/12
CPC classification number: G06F3/0412 , G02F1/13338 , G02F1/134309 , G02F1/136204 , G02F1/136286 , H01L27/124 , G06F3/044
Abstract: An array substrate and a touch display device are provided. In the array substrate, a first control unit and a second control unit are arranged opposite to each other in a first direction. A plurality of touch sensor blocks includes a first group of electrode blocks and a second group of electrode blocks arranged in the first direction, and a plurality of touch signal lines includes a first group of touch signal lines and a second group of touch signal lines arranged in the first direction. The touch signal lines in the first group of touch signal lines are coupled to the touch sensor blocks in the first group of electrode blocks respectively; and the touch signal lines in the second group of touch signal lines are coupled to the touch sensor blocks in the second group of electrode blocks respectively.
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公开(公告)号：US20230041639A1
公开(公告)日：2023-02-09
申请号：US17792264
申请日：2021-09-01
Inventor： Wenjie Hou , Yingmeng Miao , Qiujie Su , Chongyang Zhao , Feng Qu
IPC: G02F1/1362
Abstract: Provided are an array substrate and a manufacturing method thereof, and a display device. The array substrate comprises a plurality of data lines and sub-pixels. At least one sub-pixel comprises: a first insulating layer; a gate; an active layer located on one side of the first insulating layer away from the gate; a pixel electrode; a first electrode located connected to the active layer and in contact with the pixel electrode; a second electrode connected to the active layer and a data line; a second insulating layer having a first opening, wherein the orthographic projection of the first opening partially overlaps with the orthographic projections of the pixel electrode and the first electrode; a connection electrode in contact with the pixel electrode and the first electrode through the first opening; and a common electrode located on one side of the second insulating layer away from the pixel electrode.
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Patent Agency Ranking
公开(公告)号：US12292642B2
公开(公告)日：2025-05-06
申请号：US17788222
申请日：2021-09-17
Inventor： Yingying Qu , Lingdan Bo , Ting Dong , Jianhua Huang , Qiujie Su , Dongchuan Chen , Yanping Liao , Seungmin Lee , Jiantao Liu , Yue Yang
IPC: G02F1/1335 , G02F1/1333 , G02F1/1368
Abstract: The present disclosure provides a display panel and a manufacturing method therefor, and a display apparatus, which relate to the technical field of displaying. The display panel includes a first base plate and a second base plate which are aligned with each other; the first base plate includes a first substrate and a thin film transistor; the thin film transistor includes an active layer; an optical adjustment layer is disposed on the second base plate; an orthographic projection of the optical adjustment layer on the first substrate overlaps with an orthographic projection of the active layer on the first substrate. That is, the optical adjustment layer corresponds to the active layer. In a laminating direction of the display panel, the existence of the optical adjustment layer with a certain height enables a reflecting surface of the second base plate to be closer to the first base plate.
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公开(公告)号：US20240168326A1
公开(公告)日：2024-05-23
申请号：US17788222
申请日：2021-09-17
Inventor： Yingying Qu , Lingdan Bo , Ting Dong , Jianhua Huang , Qiujie Su , Dongchuan Chen , Yanping Liao , Seungmin Lee , Jiantao Liu , Yue Yang
IPC: G02F1/1335 , G02F1/1333 , G02F1/1368
CPC classification number: G02F1/133514 , G02F1/133302 , G02F1/133512 , G02F1/1368
Abstract: The present disclosure provides a display panel and a manufacturing method therefor, and a display apparatus, which relate to the technical field of displaying. The display panel includes a first base plate and a second base plate which are aligned with each other; the first base plate includes a first substrate and a thin film transistor; the thin film transistor includes an active layer; an optical adjustment layer is disposed on the second base plate; an orthographic projection of the optical adjustment layer on the first substrate overlaps with an orthographic projection of the active layer on the first substrate. That is, the optical adjustment layer corresponds to the active layer. In a laminating direction of the display panel, the existence of the optical adjustment layer with a certain height enables a reflecting surface of the second base plate to be closer to the first base plate.
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公开(公告)号：US11823640B2
公开(公告)日：2023-11-21
申请号：US17429937
申请日：2020-10-30
Inventor： Chongyang Zhao , Yingmeng Miao , Qiujie Su , Zhihua Sun , Wenjie Hou , Feng Qu
CPC classification number: G09G3/3677 , H01L27/124 , H01L27/1225
Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes: a gate driving circuitry arranged at a peripheral region of the display substrate; n clock signal leads coupled to the gate driving circuitry, each clock signal lead extending in a first direction; and n clock signal lines arranged sequentially in the first direction, each clock signal line extending in a second direction intersecting the first direction, where n is a positive integer greater than 1. The clock signal leads have a same length in the first direction, each clock signal lead extends from a first clock signal line to an nth clock signal line, and each clock signal lead is coupled to a corresponding clock signal line at a position where the clock signal lead intersects the clock signal line.
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公开(公告)号：US20230215320A1
公开(公告)日：2023-07-06
申请号：US18182479
申请日：2023-03-13
Inventor： Zhihua Sun , Yinlong Zhang , Qiujie Su , Feng Qu , Jing Liu , Yanping Liao , Xibin Shao
IPC: G09G3/20
CPC classification number: G09G3/20 , G09G2310/08 , G09G2310/0278 , G09G2310/0205
Abstract: Embodiments of the present disclosure provide a method of driving display, and a display device. The method of driving display includes: scanning, progressively or rows by rows, a plurality of sub-pixels arranged in an N×M array, to turn on each row of sub-pixels scanned, so that a duration in which two adjacent rows of sub-pixels are simultaneously in an ON state is greater than or equal to two times a unit scanning time, wherein the unit scanning time is a time required for scanning a row of sub-pixels, N is an integer greater than 1, and M is an integer greater than 1; and applying data signals to at least two rows of sub-pixels simultaneously in the ON state, so that a duration of applying the data signals to each row of sub-pixels is greater than the unit scanning time.
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公开(公告)号：US11296123B2
公开(公告)日：2022-04-05
申请号：US15779222
申请日：2017-09-29
Inventor： Ning Zhu , Qiujie Su , Chongyang Zhao
IPC: H01L27/12
Abstract: An array substrate and a manufacturing method thereof, a display panel and a display device are provided. The array substrate includes common electrodes, multiple first common electrode lines and multiple second common electrode lines. The multiple first common electrode lines intersect with the multiple second common electrode lines to form grids. The multiple first common electrode lines are connected with the common electrodes through first via-holes and the multiple second common electrode lines are connected with the common electrodes through second via-holes.
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