利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

4 条记录 (耗时 0.018 秒)

    Display Substrate, Manufacturing Method Thereof and Display Device
    1.
    发明公开
    Display Substrate, Manufacturing Method Thereof and Display Device 审中-公开

    公开(公告)号：US20240306428A1

    公开(公告)日：2024-09-12

    申请号：US18028265

    申请日：2022-04-24

    申请人： Chengdu BOE Optoelectronics Technology Co., Ltd. ,  BOE Technology Group Co., Ltd.

    发明人： Sa Liu ,  Yongyi Fu ,  Hexiong Li ,  Yong Zhou ,  Feng Bai

    IPC分类号： H10K59/122 ,  H10K59/12

    CPC分类号： H10K59/122 ,  H10K59/1201

    摘要： A display substrate, a manufacturing method thereof, and a display device are provided. The display substrate includes sub-pixels, at least part of the sub-pixels include a light emitting element, the light emitting element includes a light emitting functional layer, and a first electrode and a second electrode, the first electrode is located between the light emitting functional layer and the base substrate, and the light emitting functional layer includes film layers; the display substrate further includes a first defining structure located between at least two adjacent sub-pixels, the first defining structure includes an end portion located between the light emitting functional layer and the first electrode, and the first electrode overlaps with the end portion in the direction perpendicular to the base substrate; at least one of the film layers in at least one sub-pixel is disconnected at the end portion of the first defining structure.

    Via-hole etching method
    2.
    发明授权
    Via-hole etching method 有权
    通孔蚀刻法

    公开(公告)号：US09564354B2

    公开(公告)日：2017-02-07

    申请号：US14361083

    申请日：2013-12-03

    申请人： BOE TECHNOLOGY GROUP CO., LTD. ,  CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

    发明人： Byung Chun Lee ,  Donghua Jiang ,  Yongyi Fu ,  Wuyang Zhao ,  Chundong Li

    IPC分类号： H01L21/768 ,  H01L21/3213 ,  H01L21/311

    CPC分类号： H01L21/76804 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76895

    摘要： The present invention discloses a via-hole etching method related to semiconductor manufacturing field, and the method overcomes the defects of an uncontrollable end point of a via-hole and an unfavorable profile-angle in a conventional via-hole etching method. The via-hole etching method includes: forming a structure for via-hole etching, includes: a low-temperature poly-silicon layer, a gate insulating layer, a gate metal layer and an interlayer insulating layer, which are sequentially formed on a substrate; forming a mask layer comprising a via-hole masking pattern on the structure for via-hole etching; by using a first etching process, etching the structure for via-hole etching to a first thickness of the gate insulating layer; by using a second etching process, etching the structure for via-hole etching to etch away the remaining thickness of the gate insulating layer, and uncovering the low-temperature poly-silicon layer; removing the mask layer to form a via-hole structure.

    摘要翻译： 本发明公开了一种与半导体制造领域相关的通孔蚀刻方法，该方法克服了以往的通孔蚀刻方法中的通孔的不可控端点和不利的形状角的缺陷。 通孔蚀刻方法包括：形成用于通孔蚀刻的结构，包括：顺序地形成在基板上的低温多晶硅层，栅极绝缘层，栅极金属层和层间绝缘层 ; 在所述用于通孔蚀刻的结构上形成包括通孔掩模图案的掩模层; 通过使用第一蚀刻工艺，将用于通孔蚀刻的结构蚀刻到栅极绝缘层的第一厚度; 通过使用第二蚀刻工艺，蚀刻用于通孔蚀刻的结构以蚀刻掉栅极绝缘层的剩余厚度，并露出低温多晶硅层; 去除掩模层以形成通孔结构。