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1.发明申请公开(公告)号：US20220085339A1
公开(公告)日：2022-03-17
申请号：US17472780
申请日：2021-09-13
发明人： Zheng BAO , Kang WANG , Xiaodong HAO , Junyue YUAN , Yanxia XIN , Gong CHEN
摘要： A package structure, a method for forming a package structure, a display panel and a display device are provided. The package structure includes: a polarizing structure and a first optical adhesive layer; the polarizing structure includes a first viewing aperture corresponding to a camera; the first optical adhesive layer is arranged at a side of the polarizing structure, and at least a part of the first viewing aperture is filled with the first optical adhesive layer.
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公开(公告)号：US20220181426A1
公开(公告)日：2022-06-09
申请号：US17437033
申请日：2021-01-20
发明人： Gong CHEN , Yuqing YANG , Yiyang ZHANG , Zheng BAO , Zhiyong YANG , Yang ZHOU , Huijun LI , Tingliang LIU , Huijuan YANG , Xin ZHANG , Meng ZHANG , Xiaofeng JIANG , Hao ZHANG , Yu WANG
IPC分类号： H01L27/32
摘要： The present disclosure provides an array substrate, a method for manufacturing an array substrate and a display panel. The array substrate includes: a base having a display area, a peripheral area surrounding the display area, and a visible area located between the display area and the peripheral area; a plurality of voltage signal lines disposed on the base; a metal strip disposed on the base, the voltage signal lines are coupled to the metal strip, at least a portion of the metal strip is located in the visible area, and the portion of the metal strip located in the visible area is provided with an opening.
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公开(公告)号：US20220320240A1
公开(公告)日：2022-10-06
申请号：US17425733
申请日：2021-01-25
发明人： Zheng BAO , Gong CHEN , Kangguan PAN , Yanxia XIN , Hongwei HU , Xueping LI , Yihao WU , Xiaoyun WANG , Yong ZHUO , Zhongqian GUO
IPC分类号： H01L27/32
摘要： A display panel includes a substrate, a plurality of data lines, at least one circle of barrier wall structure, and a connector. The substrate includes a display area, and a peripheral area which surrounds the display area and includes a fan-out area. The plurality of data lines are located on one side of the substrate and in the display area, extending from the display area to the fan-out area. The at least one circle of barrier wall structure surrounds the display area, and at least a part of the at least one circle of barrier wall structure is located in the fan-out area. The connector is located between the plurality of data lines and the barrier wall structure, and one end, away from the substrate, of the connector extends into the barrier wall structure to fasten the barrier wall structure.
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公开(公告)号：US20240341140A1
公开(公告)日：2024-10-10
申请号：US18579368
申请日：2022-09-22
发明人： Haotian YANG , Xiangdong WEI , Miao LUO , Jiaming SHEN , Seungyong OH , Xiaoliang FU , Xiaoxia LIU , Kang WANG , Zheng BAO
IPC分类号： H10K59/131 , H10K59/12 , H10K102/00
CPC分类号： H10K59/131 , H10K59/1201 , H10K2102/311
摘要： The present disclosure provides a display panel and a manufacturing method therefor, and the display device. The display panel comprises a display area and a binding area, the binding area comprises a bending area and a composite circuit area which are sequentially arranged in a direction away from the display area, and the bending area is configured to turn the composite circuit area to the back of the display area by bending; a first functional hole is formed in the display area, a second functional hole is formed in the binding area, and the orthographic projection of the first functional hole on the plane of the display area at least partially overlaps the orthographic projection of the second functional hole on the plane of the display area.
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公开(公告)号：US20220344426A1
公开(公告)日：2022-10-27
申请号：US17635749
申请日：2021-03-10
发明人： Kang WANG , Xiaodong HAO , Zheng BAO
摘要： Disclosed are a display substrate and a display apparatus. The display substrate, includes base, and an organic electroluminescent display layer, a touch layer, a polarizer and a cover plate sequentially stacked on the base. The organic electroluminescent display layer and the touch layer are bonded with a first bonding layer, and the polarizer and the cover plate are bonded with a second bonding layer. The display substrate includes a camera installation area and a display area surrounding the camera installation area. A camera is installed on a side of the base away from the organic electroluminescent display layer and located in the camera installation area, a light-emitting layer is not provided in an area of the organic electroluminescent display layer corresponding to the camera installation area, and a first opening is provided in an area of the polarizer corresponding to the camera installation area.
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公开(公告)号：US20220102456A1
公开(公告)日：2022-03-31
申请号：US16771646
申请日：2020-01-06
发明人： Zheng BAO , Yaqin XIA , Yanxia XIN , Gong CHEN , Hongwei HU , Yihao WU , Xueping LI
摘要： The present application discloses embodiments of a display panel, a preparation method thereof, a detection method thereof, and a display device for improving an accuracy of detecting electrical properties of transistors. In one embodiment, a display panel may include a display area including a plurality of pixels and a non-display area surrounding the display area, wherein each of the plurality of pixels may include a display pixel circuit, and the non-display area may include one or more test pixel circuits, each of the one or more test pixel circuits having an equivalent circuit structure to the display pixel circuit, where the one or more test pixel circuits may include a plurality of transistors, and electrodes of at least one of the plurality of transistors may be respectively conductively coupled to different test pads.
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公开(公告)号：US20210408076A1
公开(公告)日：2021-12-30
申请号：US16769364
申请日：2019-06-27
发明人： Zheng BAO , Hongwei HU , Yanxia XIN , Xueping LI , Yihao WU , Gong CHEN , Peng XU
IPC分类号： H01L27/12 , G02F1/1345
摘要： Embodiments of the present disclosure provide a display substrate, a display panel, a display device, and a manufacturing method of the display substrate. The display substrate includes a display region and a peripheral region located at an outer side of the display region, and the peripheral region includes a bonding region. The display substrate includes: a base substrate, and a first metal pattern and a second metal pattern which are provided on the base substrate and located in the bonding region, the second metal pattern covers at least a portion of at least one side surface of the first metal pattern, and an activity of a metal of the second metal pattern is weaker than an activity of a metal of the first metal pattern.
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公开(公告)号：US20210020084A1
公开(公告)日：2021-01-21
申请号：US16981938
申请日：2019-12-23
IPC分类号： G09G3/00 , G02F1/1368 , H01L51/56 , H01L29/786
摘要： A test substrate has at least one test region and includes a base substrate, a plurality of thin film transistors disposed on the base substrate, at least one test hole located in the test region, and at least one test pin. At least one of the thin film transistors is a target thin film transistor to be tested, each target thin film transistor is located in one test region. Each test hole exposes a source region, a drain region or a gate of a corresponding target thin film transistor at a bottom thereof. Each test pin is located in one test hole. One end of the test pin passes through the test hole to be coupled to the source region, the drain region or the gate of the corresponding target thin film transistor, and another end of the test pin is exposed at a surface of the test substrate.
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公开(公告)号：US20240339084A1
公开(公告)日：2024-10-10
申请号：US18578731
申请日：2022-06-06
发明人： Zheng BAO , Mingqiang WANG , Ziqian LI , Yi ZHANG , Xiangdong WEI , Gong CHEN , Haotian YANG , Chang WANG , Jiaxiang ZHANG , Bin ZHANG
IPC分类号： G09G3/3275 , H10K59/12 , H10K59/121 , H10K59/131 , H10K71/60
CPC分类号： G09G3/3275 , H10K59/1201 , H10K59/1213 , H10K59/131 , H10K71/60 , G09G2300/0426 , G09G2310/08 , G09G2330/023
摘要： The present disclosure provides a display panel, a method for preparing the same, and a display device. The display panel includes pixel units distributed in an array in a display area, where the pixel units include sub-pixels, at least one of which has a maximum grayscale value voltage different from a maximum grayscale value voltage of the other sub-pixel; and a switching circuit including switching units on a side of the display area, where one end of the switching unit is connected to a data line. In two adjacent columns of pixel units, two sub-pixels having the same maximum grayscale value voltage are connected to two adjacent switching units through data lines, respectively.
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10.发明公开公开(公告)号：US20230171998A1
公开(公告)日：2023-06-01
申请号：US17921898
申请日：2021-06-01
发明人： Yong ZHUO , Yanxia XIN , Hongwei HU , Zheng BAO , Xueping LI , Yihao WU , Xiaoyun WANG , Zhongqian GUO
IPC分类号： H10K59/121 , H10K71/70 , H10K59/12 , H10K59/131
CPC分类号： H10K59/1213 , H10K71/70 , H10K59/1216 , H10K59/1201 , H10K59/131
摘要： Provided are a display substrate, a testing method therefor and a preparation method therefor, and a display panel, which are used for improving the success rate of transistor testing. The display substrate comprises a base substrate and a pixel circuit, wherein the pixel circuit comprises an active layer, a first gate insulating layer, a first gate electrode layer, a second gate insulating layer, a second gate electrode layer, a first interlayer insulating layer, a source/drain electrode layer, and a second interlayer insulating layer. The pixel circuit is divided into a plurality of transistors, and further comprises a gate electrode contact hole and a source/drain electrode contact hole. The source/drain electrode layer comprises a gate electrode test pad which is electrically connected to the first gate electrode layer by means of the gate electrode contact hole, and a source electrode and a drain electrode which are electrically connected to the active layer by means of the source/drain electrode contact hole. The second interlayer insulating layer is provided with a gate electrode test hole and a source/drain electrode test hole, wherein the gate electrode test hole exposes the gate electrode test pad, and the source/drain electrode test hole exposes part of an area in the source/drain electrode layer other than the gate electrode test pad.
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