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公开(公告)号：US20220269363A1
公开(公告)日：2022-08-25
申请号：US17497921
申请日：2021-10-09
发明人： Chengwei LI , Dayu ZHANG , Zhiwei ZHANG , Taorong WANG
摘要： Embodiments of the present disclosure disclose a touch display panel and a display device. Two touch electrode routing wires are arranged correspondingly between two adjacent data lines, a distance between the two touch electrode routing wires between the two adjacent data lines is smaller than each of distances from the touch electrode routing wires to the data lines correspondingly adjacent thereto, and the distances from the two touch electrode routing wires between the two adjacent data lines to the data lines correspondingly adjacent thereto are unequal.
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公开(公告)号：US20240212636A1
公开(公告)日：2024-06-27
申请号：US17919856
申请日：2021-10-27
发明人： Chengwei LI , Dayu ZHANG , Zhiwei ZHANG , Xinchen MA
CPC分类号： G09G3/342 , G09G3/2007 , G09G2320/0233 , G09G2320/0686 , G09G2360/16
摘要： The present application provides a brightness regulating method, a brightness regulating system and a display device, which relates to the technical field of displaying. The brightness regulating method includes: dividing the backlight module into a plurality of light areas; according to brightnesses of the light areas, determining a reference light area; according to a brightness of the reference light area, determining a compensation parameter of a to-be-compensated light area; converting the compensation parameter into compensated-grayscale data of the display panel; and according to the compensated-grayscale data, controlling a display frame corresponding to the to-be-compensated light area to display a brightness that has been updated.
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3.发明申请CLOCK SIGNAL GENERATING CIRCUIT, GATE DRIVING CIRCUIT, DISPLAY PANEL AND DISPLAY DEVICE 审中-公开时钟信号发生电路，门驱动电路，显示面板和显示设备公开(公告)号：US20160351154A1
公开(公告)日：2016-12-01
申请号：US15097480
申请日：2016-04-13
发明人： Fei XU , Zhen ZHANG , Zhiwei ZHANG
CPC分类号： G09G3/3677 , G06F1/04 , G06F1/06 , G09G2310/0286 , G09G2310/08 , G09G2330/06 , G11C19/287
摘要： A clock signal generating circuit, a gate driving circuit, a display panel and a display device are disclosed. A first clock signal terminal inputs a first clock signal to a selection module. A second clock signal terminal inputs a second clock signal to the selection module. The selection module couples a high level signal input terminal to an output terminal or disconnects the high level signal input terminal from the output terminal according to the first clock signal, and couples a low level signal input terminal to the output terminal or disconnects the low level signal input terminal from the output terminal according to the second clock signal. The selection module couples the high level signal input terminal and the low level signal input terminal alternately to the output terminal, so that the output terminal outputs a target clock signal.
摘要翻译： 公开了时钟信号发生电路，门驱动电路，显示面板和显示装置。 第一时钟信号端子将第一时钟信号输入到选择模块。 第二时钟信号端子向选择模块输入第二时钟信号。 选择模块将高电平信号输入端子耦合到输出端子，或者根据第一时钟信号从输出端子断开高电平信号输入端子，并将低电平信号输入端子耦合到输出端子或者断开低电平 根据第二时钟信号从输出端子输入信号输入端子。 选择模块将高电平信号输入端子和低电平信号输入端子交替耦合到输出端子，使得输出端子输出目标时钟信号。
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公开(公告)号：US20190206353A1
公开(公告)日：2019-07-04
申请号：US16041166
申请日：2018-07-20
发明人： Zhiwei ZHANG , Xia FENG
IPC分类号： G09G3/36
摘要： A display panel and a driving method therefor and a display apparatus are provided. The display panel includes a plurality of gate lines and a plurality of data lines, which intersect with each other, each of the data lines has an input terminal, and input terminals of the data lines are provided at a first side of the display panel, the driving method comprises: sequentially applying a gate signal to each of the gate lines, and applying data signals to the data lines through the input terminals while any of the gate lines is applied with a gate signal, wherein the gate signal satisfies conditions that Ta(i)≤Ta(i+1) and Ta(1)
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公开(公告)号：US20190355320A1
公开(公告)日：2019-11-21
申请号：US16503724
申请日：2019-07-05
发明人： Zhiwei ZHANG , Tao MA , Cheng CHEN
IPC分类号： G09G3/36
摘要： Provided are a driving method and a driving apparatus for a display device, and a display device. The driving method includes inputting a gate driving signal to each gate line progressively, and inputting a gate driving signal to one gate line within each scanning period; inputting a data signal to each data line within each scanning period, and inverting, for one time, polarity of a data signal inputted to the same data line every n scanning periods; and inputting a threshold voltage with a preset time length to a threshold voltage line within each scanning period, latching the data signal inputted to the data line when a threshold voltage is inputted to the threshold voltage line, and outputting the data signal otherwise; wherein the second time length is greater than the first time length.
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公开(公告)号：US20170213508A1
公开(公告)日：2017-07-27
申请号：US15234576
申请日：2016-08-11
发明人： Zhiwei ZHANG , Tao MA
IPC分类号： G09G3/36
CPC分类号： G09G3/3614 , G09G3/3648 , G09G3/3677 , G09G2300/04 , G09G2310/0286 , G09G2310/08
摘要： A driving apparatus is provided, including a gate driving circuit, which is connected to each of gate lines, configured to input a gate driving signal to gate lines during each scan cycle, a source driving circuit, which is configured to input a data signal to data lines during each scan cycle and invert the polarities of the data signal to a data line every preset number of scan cycles, and a output enable signal driving circuit, which is configured to input a voltage signal having a first duration to a output enable signal line in response to the polarities of the data signal being inverted during a first scan cycle, and input a voltage signal having a second duration longer than the first duration to the output enable signal line in response to the polarities of the data signal not being inverted during a second scan cycle.
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公开(公告)号：US20170132982A1
公开(公告)日：2017-05-11
申请号：US15232042
申请日：2016-08-09
发明人： Zhiwei ZHANG , Tao MA , Cheng CHEN
IPC分类号： G09G3/36
摘要： Provided are a driving method and a driving apparatus for a display device, and a display device. The driving method comprises inputting a gate driving signal to each gate line progressively, and inputting a gate driving signal to one gate line within each scanning period; inputting a data signal to each data line within each scanning period, and inverting, for one time, polarity of a data signal inputted to the same data line every n scanning periods; and inputting a threshold voltage with a preset time length to a threshold voltage line within each scanning period, latching the data signal inputted to the data line when a threshold voltage is inputted to the threshold voltage line, and outputting the data signal otherwise; wherein the second time length is greater than the first time length. Undesirable phenomena such as vertical stripes can be avoided, or improvement can be made thereto.
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