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公开(公告)号：US20230163200A1
公开(公告)日：2023-05-25
申请号：US17771720
申请日：2021-03-08
Inventor： Xinguo WU , Fengguo WANG , Liang TIAN , Yu FENG , Bin LIU , Chenglong WANG , Yuxuan MA
IPC: H01L29/66 , H01L29/786
CPC classification number: H01L29/6675 , H01L29/78696 , H01L29/78672
Abstract: A method for manufacturing a display substrate is provided. The method includes: forming a first active layer arranged in the NMOS transistor region and a second active layer arranged in the PMOS transistor region on the base substrate; coating one side, facing away from the base substrate, of the first active layer and one side, facing away from the base substrate, of the second active layer with a first photoresist layer, forming a first pattern layer by patterning the first photoresist layer to expose at least two ends of the first active layer; forming N-type heavily doped regions by performing N-type heavy doping on the two ends of the first active layer with the first pattern layer as a mask; forming a second pattern layer by processing the first pattern layer to expose at least a middle region of the first active layer.
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公开(公告)号：US20230154933A1
公开(公告)日：2023-05-18
申请号：US17622708
申请日：2021-01-29
Applicant: BOE Technology Group Co., Ltd.
Inventor： Jiguo WANG , Jian SUN , Zhao ZHANG , Liang TIAN , Weida QIN , Zhen WANG , Han ZHANG , Wenwen QIN , Xiaoyan YANG , Yue SHAN , Wei YAN , Jian ZHANG , Deshuai WANG , Yadong ZHANG , Jiantao LIU
IPC: H01L27/12 , G02F1/1362 , G02F1/1368
CPC classification number: H01L27/124 , G02F1/13629 , G02F1/136213 , H01L27/1255 , G02F1/1368 , G02F1/136209 , G02F1/136222
Abstract: An array substrate includes: a first substrate (10), including a plurality of sub-pixel regions (101) arranged in an array along a row direction (X) and a column direction (Y); a pixel circuit layer, including a plurality of sub-pixel circuits; a planarization layer (17), provided with a first via hole (170) located in the sub-pixel regions (101), and includes at least one pattern portion (171), the pattern portion (171) includes a plurality of pattern units (171a) arranged in an array along the row direction (X) and the column direction (Y); and a reflective electrode layer, wherein the reflective electrode layer includes a plurality of reflective electrodes (18) that are mutually disconnected, each of the reflective electrodes (18) is located in one of the sub-pixel regions (101) and is electrically connected to the sub-pixel circuit through the first via hole (170).
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3.发明申请公开(公告)号：US20200303560A1
公开(公告)日：2020-09-24
申请号：US16601991
申请日：2019-10-15
Inventor： Zhixuan GUO , Fengguo WANG , Yezhou FANG , Xinguo WU , Hong LIU , Kai LI , Liang TIAN , Shiyu ZHANG
IPC: H01L29/786 , H01L29/66
Abstract: A thin film transistor, a method for fabricating the same, an array substrate, a display panel, and a display device are provided. The thin film transistor includes a substrate, and an active layer on the substrate, wherein the active layer includes a poly-silicon layer and has a channel region and two electrode connection regions respectively on two sides of the channel region, and the channel region includes a plurality of lightly drain doping segments, which are spaced apart along from one of the electrode connection regions to the other electrode connection region, and channel segments located between the lightly drain doping segments.
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公开(公告)号：US20200212071A1
公开(公告)日：2020-07-02
申请号：US16640940
申请日：2019-03-22
Inventor： Zhixuan GUO , Fengguo WANG , Yezhou FANG , Feng LI , Xinguo WU , Hong LIU , Zifeng WANG , Lei LI , Feng LI , Kai LI , Liang TIAN , Jing ZHAO , Zhengkui WANG , Bo MA , Haiqin LIANG , Peng LIU
Abstract: The present disclosure relates to the technical field of display. Disclosed are an array substrate and a preparation method therefor, and a display panel and a display device. The array substrate includes: a substrate; multiple gate lines, wherein the gate lines are located on the substrate, and extend along a first direction; multiple data lines, wherein the data lines are located on the substrate, and extend along a second direction, and the gate lines and the data lines intersect to define multiple pixel areas; and a touch-control electrode wiring wherein the touch-control electrode wiring has the same direction as that of the gate lines, and is arranged insulated from the gate lines on a different layer, and the orthographic projection of the touch-control electrode wiring on the substrate at least has an overlapping area with the orthographic projection of part of the gate lines on the substrate.
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Patent Agency Ranking
公开(公告)号：US20230018774A1
公开(公告)日：2023-01-19
申请号：US17626765
申请日：2021-03-10
Inventor： Xinguo WU , Fengguo WANG , Hong LIU , Yu FENG , Liang TIAN , Haidong WANG , Shicheng SONG
IPC: H01L27/12
Abstract: The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a base substrate and a plurality of pixels arranged on the base substrate, each pixel includes a plurality of sub-pixels, and each sub-pixel includes a first active layer, a first gate insulation layer, a gate electrode, a second gate insulation layer, a second active layer, a first insulation layer, a source electrode and a drain electrode laminated one on another. The source electrode is connected with the first active layer through a via hole penetrating through the first insulation layer, the second gate insulation layer and the first gate insulation layer, and the source electrode and the drain electrode are connected with the second active layer through a via hole penetrating through the first insulation layer.
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公开(公告)号：US20210157185A1
公开(公告)日：2021-05-27
申请号：US16811122
申请日：2020-03-06
Inventor： Hong LIU , Yezhou FANG , Fengguo WANG , Xinguo WU , Zhixuan GUO , Haidong WANG , Liang TIAN , Kai LI , Bo MA
IPC: G02F1/1368 , G02F1/1362
Abstract: An array substrate, a display panel including the same, and a display device are provided. The array substrate includes: a base substrate and a planarization layer on the base substrate. A first conductive layer is disposed on a side of the planarization layer away from the base substrate. A first passivation layer is disposed on a side of the first conductive layer and the side of the planarization layer not being covered by the first conductive layer, away from the base substrate, and provided with a plurality of stress release openings. An insulating layer is disposed in the stress release openings and on a side of the first passivation layer away from the planarization layer. A second conductive layer is disposed on a side of the insulating layer away from the planarization layer.
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公开(公告)号：US20200348784A1
公开(公告)日：2020-11-05
申请号：US16763105
申请日：2019-04-15
Inventor： Xinguo WU , Fengguo WANG , Zhixuan GUO , Hong LIU , Bo MA , Kai LI , Liang TIAN , Shicheng SONG
IPC: G06F3/041
Abstract: A touch display substrate includes a common electrode, a common electrode line connected to the common electrode, a touch electrode, and a touch signal line connected to the touch electrode, wherein the common electrode is multiplexed as the touch electrode, and the common electrode line is multiplexed as the touch signal line, wherein the touch display substrate further comprises an inorganic insulation layer arranged between the touch electrode and the touch signal line, the touch electrode is electrically connected to the touch signal line through a via-hole penetrating through the inorganic insulation layer, and the touch electrode, the inorganic insulation layer and the touch signal line are stacked in sequence.
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公开(公告)号：US20240258335A1
公开(公告)日：2024-08-01
申请号：US18630971
申请日：2024-04-09
Applicant: BOE Technology Group Co., Ltd.
Inventor： Jiguo WANG , Jian SUN , Zhao ZHANG , Liang TIAN , Weida QIN , Zhen WANG , Han ZHANG , Wenwen QIN , Xiaoyan YANG , Yue SHAN , Wei YAN , Jian ZHANG , Deshuai WANG , Yadong ZHANG , Jiantao LIU
IPC: H01L27/12 , G02F1/1362 , G02F1/1368
CPC classification number: H01L27/124 , G02F1/136209 , G02F1/136213 , G02F1/136222 , G02F1/13629 , G02F1/1368 , H01L27/1255
Abstract: An array substrate includes: a first substrate (10), including a plurality of sub-pixel regions (101) arranged in an array along a row direction (X) and a column direction (Y); a pixel circuit layer, including a plurality of sub-pixel circuits; and a planarization layer (17), provided with a first via hole (170) located in the sub-pixel regions (101), and includes at least one pattern portion (171), the pattern portion (171) includes a plurality of pattern units (171a) arranged in an array along the row direction (X) and the column direction (Y); where the pattern unit (171a) further includes a second bump (1712) located within a central area surrounded by each of the first bumps (1710), and the spacing groove (1711) on a same side of the first bump (1710) and the second bump (1712) is arranged in a non-straight shape.
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公开(公告)号：US20240250090A1
公开(公告)日：2024-07-25
申请号：US18014393
申请日：2021-12-16
Inventor： Bin LIU , Hong LIU , Xinguo WU , Fengguo WANG , Wenqiang LV , Yu FENG , Liang TIAN , Yuxuan MA , Bo MA
IPC: H01L27/12 , G02F1/1333 , G02F1/1343 , G02F1/1362 , G02F1/1368 , G06F3/041 , G06F3/044
CPC classification number: H01L27/124 , G02F1/13338 , G02F1/134372 , G02F1/136209 , G02F1/136286 , G02F1/1368 , G06F3/0412 , G06F3/0445 , G06F3/0418 , G06F2203/04103 , G06F2203/04107
Abstract: A display substrate and a display device are provided. The display substrate includes: a base substrate and a plurality of sub-pixels distributed in arrays and provided on the base substrate. And the plurality of sub-pixels is divided into a plurality of sub-pixel columns. The display substrate further includes: a plurality of data lines, each of which is coupled to respective sub-pixels at a corresponding sub-pixel column; a plurality of touch electrodes and a plurality of touch signal lines coupled to corresponding touch electrodes. Specifically an orthogonal projection of each of the touch signal lines on the base substrate is adjacent to an orthogonal projection of a corresponding data line among the plurality of data lines on the base substrate, and each of the touch signal lines comprises first touch portions and second touch portions coupled to each other, the first touch portions and the second touch portions being arranged in different layers, and the second touch portions being of the same material and provided in a same layer as the data lines.
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