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公开(公告)号：US20200242996A1
公开(公告)日：2020-07-30
申请号：US16714385
申请日：2019-12-13
Inventor： Zhen WANG , Han ZHANG , Zhengkui WANG , Wei YAN , Yun QIAO , Wenwen QIN , Xiaozhou ZHAN , Jian SUN , Jian ZHANG , Deshuai WANG
IPC: G09G3/20
Abstract: A display panel, a display device and a display control method thereof are provided in the present disclosure. The display panel includes: a time division multiplexing multiplexer (MUX) signal input circuit, which is connected with each of the plurality of signal lines, and configured to input data signals of each frame of display image to the plurality of signal lines, and for each frame of display image, input trigger signals corresponding to sub-pixel units of different colors to the plurality of signal lines in a time-sharing manner; among the plurality of signal lines, electrical signals on a plurality of adjacent first signal lines are arranged in sequence according to an order of positive, positive, negative and negative; among the plurality of signal lines, a first signal line has a spacing distance from adjacent signal lines less than a preset value.
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公开(公告)号：US20200211486A1
公开(公告)日：2020-07-02
申请号：US16547787
申请日：2019-08-22
Inventor： Zhen WANG , Wenwen QIN , Mingchao MA , Wenchao HAN , Jian SUN , Yun QIAO , Jun FAN
IPC: G09G3/36
Abstract: An array substrate, a display panel, a display device, and driving methods thereof are provided. The array substrate includes a plurality of subpixels arranged in an array, a plurality of data lines, and a plurality of switches. The plurality of subpixels include subpixels of a first color, subpixels of a second color, subpixels of a third color, and subpixels of a fourth color, in odd rows of subpixels, the subpixels of the first color, the subpixels of the second color, the subpixels of the third color, and the subpixels of the fourth color are sequentially arranged; in even rows of subpixels, the subpixels of the third color, the subpixels of the fourth color, the subpixels of the first color, and the subpixels of the second color are sequentially arranged; and each column of subpixels corresponds to and is connected with a data line.
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3.发明申请公开(公告)号：US20200241723A1
公开(公告)日：2020-07-30
申请号：US16642007
申请日：2019-05-31
Inventor： Wenwen QIN , Jian SUN , Yun QIAO , Xiaozhou ZHAN , Han ZHANG , Zhen WANG , Lele CONG , Zhengkui WANG
IPC: G06F3/041
Abstract: A touch array baseplate panel, including a substrate and a film layer structure. The film layer structure includes: a touch electrode layer, including a plurality of touch electrodes arranged in an array; a first electrically conductive layer, including a plurality of touch electrode lines and virtual touch electrode lines; a second electrically conductive layer, including connection lines. A touch electrode line is electrically connected to a corresponding touch electrode through a first via hole, and a virtual touch electrode line is electrically connected to a corresponding touch electrode through a second via hole, and a connection line electrically connects, through third via holes, a touch electrode line and a virtual touch electrode line electrically connected to a same touch electrode. This disclosure further provides a method for manufacturing the touch array baseplate panel and a touch panel including the touch array baseplate panel.
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公开(公告)号：US20190235294A1
公开(公告)日：2019-08-01
申请号：US16180419
申请日：2018-11-05
Inventor： Zhengkui WANG , Jian SUN , Fei HUANG , Jiguo WANG , Yun QIAO , Xiaozhou ZHAN , Han ZHANG , Zhen WANG , Wenwen QIN , Lele CONG , Peng LIU , Jianjun ZHANG
IPC: G02F1/1333 , G02F1/1362 , G02F1/1368 , G06F3/044 , G06F3/041
Abstract: An array substrate includes a base substrate, a plurality of first signal lines extending in a first direction, a plurality of second signal lines located on a different layer from the first signal lines and extending in a second direction intersecting the first direction, and a plurality of touch signal lines extending in the second direction disposed on the base substrate. Each touch signal line includes a first touch line segment and a second touch line segment, the first touch line segment disposed on the same layer as the first signal lines, and at least partially overlapping with at least one of the second signal lines in a direction perpendicular to a surface of the base substrate, the second touch line segment disposed on a different layer from the first signal lines, and the first touch line segment electrically connected with the second touch line segment through a first via.
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公开(公告)号：US20210357094A1
公开(公告)日：2021-11-18
申请号：US16476621
申请日：2019-01-10
Inventor： Yun QIAO , Zhen WANG , Xiaozhou ZHAN , Han ZHANG , Wenwen QIN , Peng LIU , Zhengkui WANG
Abstract: A wiring structure includes a plurality of first connection lines disposed in a first wiring layer and extending respectively from first ones of the plurality of first electrical contacts to first ones of the plurality of second electrical contacts, the first connection lines not intersecting each other; and a plurality of second connection lines disposed in a second wiring layer and extending respectively from second ones of the plurality of first electrical contacts to second ones of the plurality of second electrical contacts, the second connection lines not intersecting each other. An orthographic projection of any one of the first connection lines onto a plane parallel to the first and second wiring layers does not intersect an orthographic projection of any one of the second connection lines onto the plane.
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Patent Agency Ranking
公开(公告)号：US20210149262A1
公开(公告)日：2021-05-20
申请号：US16642596
申请日：2019-01-04
Inventor： Yun QIAO , Han ZHANG , Kai CHEN , Zhen WANG , Zhengkui WANG , Wenwen QIN , Wei YAN , Jian ZHANG , Xiaozhou ZHAN , Deshuai WANG , Jian SUN
IPC: G02F1/1362 , G02F1/1339
Abstract: A liquid crystal display panel and a display device. The liquid crystal display panel includes a display region and an opening region in the display region; the display region includes a plurality of sub-pixels, the display region includes a first edge and a second edge opposite to the first edge, the display region includes a first region between the opening region and the first edge and a second region between the opening region and the second edge, an orthographic projection of the opening region on the first edge respectively coincides with orthographic projections of the first region and the second region on the first edge, the plurality of sub-pixels comprise a main sub-pixel in the first region and a secondary sub-pixel in the second region, and an area of the main sub-pixel is smaller than an area of the secondary sub-pixel.
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公开(公告)号：US20210142747A1
公开(公告)日：2021-05-13
申请号：US17153120
申请日：2021-01-20
Inventor： Zhen WANG , Wenwen QIN , Mingchao MA , Wenchao HAN , Jian SUN , Yun QIAO , Jun FAN
IPC: G09G3/36
Abstract: An array substrate, a display panel, a display device, and driving methods thereof are provided. The array substrate includes subpixels arranged in an array, and switches. The subpixels include subpixels of a first color, subpixels of a second color, subpixels of a third color, subpixels of a fourth color, in odd rows of subpixels, the subpixels of the first color, the subpixels of the second color, the subpixels of the third color, the subpixels of the fourth color are sequentially arranged; in even rows of subpixels, the subpixels of the third color, the subpixels of the fourth color, the subpixels of the first color, the subpixels of the second color are sequentially arranged; and the subpixels of the first color are white subpixels; the subpixels of the second color are blue subpixels; the subpixels of the third color are green subpixels; the subpixels of the fourth color are red subpixels.
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公开(公告)号：US20250166542A1
公开(公告)日：2025-05-22
申请号：US19023209
申请日：2025-01-15
Applicant: BOE Technology Group Co., Ltd.
Inventor： Wei YAN , Zhen WANG , Wenwen QIN , Han ZHANG , Deshuai WANG , Jian ZHANG , Yue SHAN , Xiaoyan YANG , Yadong ZHANG , Jian SUN
Abstract: A shift register and a driving method therefor, a gate driving circuit and a display device are provided, wherein the shift register includes a pull-up control sub-circuit configured to provide a signal of a first signal terminal or a second signal terminal to a pull-up control node under control of a first input terminal and a second output terminal; the pull-down control sub-circuit is configured to provide a signal of a first power supply terminal or a second power supply terminal to a pull-down node under control of the pull-up control node, the first signal terminal, the second signal terminal, a first clock signal terminal and a second clock signal terminal; the output sub-circuit is configured to supply a signal of a third clock signal terminal to a first output terminal and a signal of a fourth clock signal terminal to the second output terminal.
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公开(公告)号：US20230395008A1
公开(公告)日：2023-12-07
申请号：US18032512
申请日：2020-10-21
Applicant: BOE Technology Group Co., Ltd.
Inventor： Wei YAN , Wenwen QIN , Yue SHAN , Deshuai WANG , Jiguo WANG , Zhen WANG , Xiaoyan YANG , Han ZHANG , Jian ZHANG , Yadong ZHANG , Jian SUN
CPC classification number: G09G3/20 , G11C19/28 , G09G2310/0286
Abstract: A shift register unit, a driving method, a drive circuit, and a display apparatus are disclosed. The shift register unit includes: a control circuit, which is configured to adjust signals of a first node and a second node according to an input signal end, a first control signal end, a second control signal end and a first reference signal end; a cascade circuit, which is configured to provide, according to the signal of the first node, a signal of a first cascade clock signal end to a cascade output end; and an output circuit, which is configured to provide, according to the signal of the first node, a signal of a control clock signal end to a drive output end, and provide, according to the signal of the second node, a signal of a second reference signal end to the drive output end.
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公开(公告)号：US20230154933A1
公开(公告)日：2023-05-18
申请号：US17622708
申请日：2021-01-29
Applicant: BOE Technology Group Co., Ltd.
Inventor： Jiguo WANG , Jian SUN , Zhao ZHANG , Liang TIAN , Weida QIN , Zhen WANG , Han ZHANG , Wenwen QIN , Xiaoyan YANG , Yue SHAN , Wei YAN , Jian ZHANG , Deshuai WANG , Yadong ZHANG , Jiantao LIU
IPC: H01L27/12 , G02F1/1362 , G02F1/1368
CPC classification number: H01L27/124 , G02F1/13629 , G02F1/136213 , H01L27/1255 , G02F1/1368 , G02F1/136209 , G02F1/136222
Abstract: An array substrate includes: a first substrate (10), including a plurality of sub-pixel regions (101) arranged in an array along a row direction (X) and a column direction (Y); a pixel circuit layer, including a plurality of sub-pixel circuits; a planarization layer (17), provided with a first via hole (170) located in the sub-pixel regions (101), and includes at least one pattern portion (171), the pattern portion (171) includes a plurality of pattern units (171a) arranged in an array along the row direction (X) and the column direction (Y); and a reflective electrode layer, wherein the reflective electrode layer includes a plurality of reflective electrodes (18) that are mutually disconnected, each of the reflective electrodes (18) is located in one of the sub-pixel regions (101) and is electrically connected to the sub-pixel circuit through the first via hole (170).
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