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公开(公告)号：US20200327949A1
公开(公告)日：2020-10-15
申请号：US15776980
申请日：2017-09-21
Inventor： Mingchao MA , Jun FAN , Yue SHAN
Abstract: The present disclosure provides a shift register unit whose operating time includes a plurality of multi-frame periods, each of the multi-frame periods including a plurality of frame periods. The shift register unit includes a trigger signal input terminal, an input circuit, a pull-up circuit, a pull-down control circuit, a plurality of pull-down circuits, and a signal output terminal. The pull-down control circuit is configured to sequentially provide active signals to the control terminals of respective pull-down circuits in pull-down stages of respective frame periods of one multi-frame period. The present disclosure further provides a shift register, a gate driving circuit and a display panel.
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公开(公告)号：US20250166542A1
公开(公告)日：2025-05-22
申请号：US19023209
申请日：2025-01-15
Applicant: BOE Technology Group Co., Ltd.
Inventor： Wei YAN , Zhen WANG , Wenwen QIN , Han ZHANG , Deshuai WANG , Jian ZHANG , Yue SHAN , Xiaoyan YANG , Yadong ZHANG , Jian SUN
Abstract: A shift register and a driving method therefor, a gate driving circuit and a display device are provided, wherein the shift register includes a pull-up control sub-circuit configured to provide a signal of a first signal terminal or a second signal terminal to a pull-up control node under control of a first input terminal and a second output terminal; the pull-down control sub-circuit is configured to provide a signal of a first power supply terminal or a second power supply terminal to a pull-down node under control of the pull-up control node, the first signal terminal, the second signal terminal, a first clock signal terminal and a second clock signal terminal; the output sub-circuit is configured to supply a signal of a third clock signal terminal to a first output terminal and a signal of a fourth clock signal terminal to the second output terminal.
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公开(公告)号：US20230395008A1
公开(公告)日：2023-12-07
申请号：US18032512
申请日：2020-10-21
Applicant: BOE Technology Group Co., Ltd.
Inventor： Wei YAN , Wenwen QIN , Yue SHAN , Deshuai WANG , Jiguo WANG , Zhen WANG , Xiaoyan YANG , Han ZHANG , Jian ZHANG , Yadong ZHANG , Jian SUN
CPC classification number: G09G3/20 , G11C19/28 , G09G2310/0286
Abstract: A shift register unit, a driving method, a drive circuit, and a display apparatus are disclosed. The shift register unit includes: a control circuit, which is configured to adjust signals of a first node and a second node according to an input signal end, a first control signal end, a second control signal end and a first reference signal end; a cascade circuit, which is configured to provide, according to the signal of the first node, a signal of a first cascade clock signal end to a cascade output end; and an output circuit, which is configured to provide, according to the signal of the first node, a signal of a control clock signal end to a drive output end, and provide, according to the signal of the second node, a signal of a second reference signal end to the drive output end.
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公开(公告)号：US20230154933A1
公开(公告)日：2023-05-18
申请号：US17622708
申请日：2021-01-29
Applicant: BOE Technology Group Co., Ltd.
Inventor： Jiguo WANG , Jian SUN , Zhao ZHANG , Liang TIAN , Weida QIN , Zhen WANG , Han ZHANG , Wenwen QIN , Xiaoyan YANG , Yue SHAN , Wei YAN , Jian ZHANG , Deshuai WANG , Yadong ZHANG , Jiantao LIU
IPC: H01L27/12 , G02F1/1362 , G02F1/1368
CPC classification number: H01L27/124 , G02F1/13629 , G02F1/136213 , H01L27/1255 , G02F1/1368 , G02F1/136209 , G02F1/136222
Abstract: An array substrate includes: a first substrate (10), including a plurality of sub-pixel regions (101) arranged in an array along a row direction (X) and a column direction (Y); a pixel circuit layer, including a plurality of sub-pixel circuits; a planarization layer (17), provided with a first via hole (170) located in the sub-pixel regions (101), and includes at least one pattern portion (171), the pattern portion (171) includes a plurality of pattern units (171a) arranged in an array along the row direction (X) and the column direction (Y); and a reflective electrode layer, wherein the reflective electrode layer includes a plurality of reflective electrodes (18) that are mutually disconnected, each of the reflective electrodes (18) is located in one of the sub-pixel regions (101) and is electrically connected to the sub-pixel circuit through the first via hole (170).
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Patent Agency Ranking
公开(公告)号：US20240258335A1
公开(公告)日：2024-08-01
申请号：US18630971
申请日：2024-04-09
Applicant: BOE Technology Group Co., Ltd.
Inventor： Jiguo WANG , Jian SUN , Zhao ZHANG , Liang TIAN , Weida QIN , Zhen WANG , Han ZHANG , Wenwen QIN , Xiaoyan YANG , Yue SHAN , Wei YAN , Jian ZHANG , Deshuai WANG , Yadong ZHANG , Jiantao LIU
IPC: H01L27/12 , G02F1/1362 , G02F1/1368
CPC classification number: H01L27/124 , G02F1/136209 , G02F1/136213 , G02F1/136222 , G02F1/13629 , G02F1/1368 , H01L27/1255
Abstract: An array substrate includes: a first substrate (10), including a plurality of sub-pixel regions (101) arranged in an array along a row direction (X) and a column direction (Y); a pixel circuit layer, including a plurality of sub-pixel circuits; and a planarization layer (17), provided with a first via hole (170) located in the sub-pixel regions (101), and includes at least one pattern portion (171), the pattern portion (171) includes a plurality of pattern units (171a) arranged in an array along the row direction (X) and the column direction (Y); where the pattern unit (171a) further includes a second bump (1712) located within a central area surrounded by each of the first bumps (1710), and the spacing groove (1711) on a same side of the first bump (1710) and the second bump (1712) is arranged in a non-straight shape.
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公开(公告)号：US20240212772A1
公开(公告)日：2024-06-27
申请号：US17794991
申请日：2021-09-28
Applicant: BOE Technology Group Co., Ltd.
Inventor： Wei YAN , Zhen WANG , Wenwen QIN , Han ZHANG , Deshuai WANG , Jian ZHANG , Yue SHAN , Xiaoyan YANG , Yadong ZHANG , Jian SUN
CPC classification number: G11C19/28 , G09G3/20 , G09G2310/0286
Abstract: A shift register and a driving method therefor, a gate driving circuit and a display device are provided, wherein the shift register includes a pull-up control sub-circuit configured to provide a signal of a first signal terminal or a second signal terminal to a pull-up control node under control of a first input terminal and a second output terminal; the pull-down control sub-circuit is configured to provide a signal of a first power supply terminal or a second power supply terminal to a pull-down node under control of the pull-up control node, the first signal terminal, the second signal terminal, a first clock signal terminal and a second clock signal terminal; the output sub-circuit is configured to supply a signal of a third clock signal terminal to a first output terminal and a signal of a fourth clock signal terminal to the second output terminal.
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7.发明申请公开(公告)号：US20200286570A1
公开(公告)日：2020-09-10
申请号：US16339752
申请日：2018-09-14
Inventor： Yue SHAN , Jiguo WANG , Jun FAN
Abstract: A shift register and a corresponding driving method, a gate driving circuit and a display device, the shift registers includes an input and reset circuit, a first output circuit, a second output circuit, a first pull-down circuit and a second pull-down circuit; the first output circuit and the second output circuit output gate driving signals according to potentials at a first clock signal terminal and a second clock signal terminal respectively, the first pull-down circuit and the second pull-down circuit reset potentials at a pull up node, a first output terminal a second output terminal according to potentials at a first pull-down node a second pull-down node respectively.
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公开(公告)号：US20200185964A1
公开(公告)日：2020-06-11
申请号：US16640211
申请日：2019-03-20
Inventor： Yanwei REN , Yue SHAN , Yu FENG , Min LIU
IPC: H02J50/10 , G02F1/1345 , G02F1/1343 , G02F1/1333 , G02F1/1362 , G02F1/1335 , H02J7/02 , G06F3/041
Abstract: A display substrate, a display device and a wireless charging method are provided. The display substrate includes: a display area and a peripheral area located outside the display area. The peripheral area includes a circuit binding area. The display substrate includes a base substrate and a wireless charging antenna disposed on the base substrate. The wireless charging antenna includes a power receiving coil and a connection lead. The connection lead is connected to the power receiving coil, and the power receiving coil is connected to the circuit binding area.
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公开(公告)号：US20180342187A1
公开(公告)日：2018-11-29
申请号：US15759722
申请日：2017-09-13
Inventor： Yue SHAN , Jun FAN , Jiguo WANG , Yishan FU , Mingchao MA
CPC classification number: G09G3/20 , G09G2310/0286 , G09G2310/06 , G11C19/28 , G11C19/287
Abstract: A shift register, a gate driving circuit, a display panel and a driving method. The shift register includes: an input circuit, an output circuit, a pull-up-node pull-down circuit, a first control circuit, a second control circuit and an output pull-down circuit. The first control circuit is configured to write a fourth clock signal into a first pull-down node and write a first power voltage into a second pull-down node responsive to a first control signal, and to write the first power voltage into the first pull-down node responsive to a voltage of a pull-up node. The second control circuit is configured to write the fourth clock signal into the second pull-down node and write the first power voltage into the first pull-down node responsive to a second control signal, and to write the first power voltage into the second pull-down node responsive to the voltage of the pull-up node.
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